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Details, datasheet, quote on part number:AD53508JP
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| Part: | AD53508JP |
| Category: | Power Management => Supervisory Circuits |
| Description: | The AD53508 is a Dual Channel Parametric Measurement Circuit With Five Current Measurement Ranges And Output Voltage Range of -4V to +9V |
| Company: | Analog Devices |
| Datasheet: | Download AD53508JP datasheet File size : 128 kB |
| Request For quote: | Find where to buy AD53508JP
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Datasheet text preview:
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FEATURES Dual Measurement Channels Precision Four-Quadrant-Per-Pin V/I Source Programmable Current Force Ranges 204.8 A and 2.048 mA Five Current Measurement Ranges 204.8 nA to 2.048 mA Output Voltage Range: 4 V to +9 V Power Supplies: +15 V, +5 V, and 10 V 44-Lead Plastic J-Leaded Chip Carrier Package APPLICATIONS Can Be Used with the AD53032 DCL to Extend Current Force Range to 35 mA GENERAL DESCRIPTION
PPMU Circuit AD53508
The device provides a remote force/sense capability to ensure accuracy at the tester pin. A guard output is available to drive the shield of a force/sense pair. Two input references per channel permit controlled switching to different voltage or current levels. The forced voltage or current levels can be switched back to the measurement system to read back the analog levels for system calibration. The circuit is powered by +15 V, +5 V and 10 V supplies and dissipates 230 mW nominally.
Recommended Use of the PPMU with AD53032 DCL
The AD53508 is a custom dual-channel parametric measurement circuit for use in semiconductor automatic test equipment. It contains programmable modes to force a pin voltage and measure its current or to integrate and hold a current value. Alternatively, a current can be forced and the compliance voltage measured.
The PPMU can be used with the AD53032 DCL to extend the Current Force Range beyond 2 mA VCOM can be set to the maximum spec allowance of 8 V, which would allow the maximum Current Force of IOL of 35 mA. The combination of the PPMU and the DCL would have a few benefits including: 1. Accurately measuring low currents. 2. Can take parallel measurements by using one PMU per pin.
FUNCTIONAL BLOCK DIAGRAM
S8 S9 EXT RC MAIN S10 VF IF DSR +2.5V S2 OUTPUT S1 MEAS OUT CON 1.25R R GUARD S18 GUARD S3 VM IM S4 S5 1.25R DIFF R INTEGRATE 2k 1 mA 2 0k 1 00 A 40pF C1 R1 R2 INT/IM
SENSE
AD53508
DAC1 DAC2 S6 S7 ENABLE
SENSE
S11 S12 S13 S14 S15 S16 S17
FORCE
UNITY
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999
AD53508SPECIFICATIONS (T = 25 C, rated power supplies unless otherwise noted)
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Parameter VOLTAGE FORCE/MEASURE MODE Voltage Swing, ± 2 mA Range ± 2 mA Drive ± 100 µA Drive ACCURACY Gain (± 0.1% Tolerance) Offset Error Gain Nonlinearity (Relative to Endpoints) Current Measure CMRR (at MEAS_OUT) DRIFT Gain Error Temperature Coefficient Offset Drift CURRENT FORCE/MEASURE MODE RANGES 0 (High) 1 (Low) ACCURACY--HIGH RANGE Transconductance (± 3% Tolerance) Transresistance (± 3% Tolerance) Offset Error Gain Nonlinearity (Relative to Endpoints) Output Compliance Voltage-Induced Transconductance/Error DRIFT--HIGH RANGE Gain Error Temperature Coefficient Offset Drift ACCURACY--LOW RANGE Transconductance (± 3% Tolerance) Transresistance (± 3% Tolerance) Offset Error Gain Nonlinearity (Relative to Endpoints) Output Compliance Voltage-Induced Transconductance/Error DRIFT--LOW RANGE Gain Error Temperature Coefficient Offset Drift CURRENT MEASURE INTEGRATE MODE RANGES High Medium Low ACCURACY--HIGH RANGE Transresistance Error (± 3% Tolerance) Offset Error Gain Nonlinearity (Relative to Endpoints) Output Compliance Voltage-Induced Transresistance Error DRIFT--HIGH RANGE Gain Error Temperature Coefficient Offset Drift ACCURACY--MEDIUM RANGE Transresistance Error (± 3% Tolerance) Offset Error Gain Nonlinearity (Relative to Endpoints) Output Compliance Voltage-Induced Transresistance Error DRIFT-- MEDIUM RANGE Gain Error Temperature Coefficient Offset Drift
Condition
Min
Typ
Max
Unit1
4 5 0.999
+9 +12 1.001 ± 15 ± 0.02 ± 0.31 ± 20 ± 100 ± 2.0 ± 200
V V V/V mV % of Span mV/V ppm (PV or MV)/°C µV/°C mA µA
Force Mode Measure Mode
0.776 1.21
0.8 1.25
0.824 1.29 ± 40 ± 0.05 +0.4 +10/60 ± 400
mA/V V/mA µA % of Span µA/V ppm (PV or MV)/°C nA/° C µA/V V/mA µA % of Span µA/V ppm (PV or MV)/°C nA/° C µA µA nA
Force Mode
0.2
Force Mode Measure Mode
77.6 12.1
80 12.5
82.4 12.9 ±4 ± 0.05 +0.04 +10/60 ± 40
Force Mode
0.02
± 20.0 ± 2.0 ± 200 0.121 0.125 0.129 ± 400 ± 0.05 ± 2.5 ± 20 ±2 1.21 1.25 1.29 ± 40 ± 0.05 ± 0.25 ± 20 ± 250
V/µA nA % of Span nA/V of Output ppm MV/°C nA/° C V/µA nA % of Span nA/V of Output ppm MV/°C p A /° C
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Parameter ACCURACY--LOW RANGE Transresistance Error (± 3% Tolerance) Offset Error Gain Nonlinearity (Relative to Endpoints) Output Compliance Voltage-Induced Transresistance Error DRIFT--LOW RANGE Gain Error Temperature Coefficient Offset Drift DISABLE MODE2 Voltage Swing, ± 2 mA Range ± 2 mA Drive ± 100 µA Drive ACCURACY Gain (± 0.1% Tolerance) Offset Error Gain Nonlinearity (Relative to Endpoints) Current Measure CMRR (at MEAS_OUT) DRIFT Gain Error Temperature Coefficient Offset Drift OTHER SPECIFICATIONS Power Supply Rejection Ratio f < 40 Hz, VCC f < 40 Hz, VEE f = 40 kHz, VCC f = 40 kHz, VEE TAMB = +70°C 70 60 35 25 ± 1.2 ± 0.02 CLOAD = 100 pF CLOAD = 2000 pF ZLOAD = 100 pF 50 k CLOAD = 20 pF Any Output Except Guards 8.5 2.5 65 25 20 2 50 2 20 10 0 ± 1.0 2.4 0.8 10 14.0 10.5 4.75 5 15 15.0 10.0 5.0 15.75 9.0 5.25 15 5 8 Condition Min 0.0121 Typ 0.0125 Max 0.0129 ±4 ± 0.05 ± 0.025 ± 20 ± 70 Unit1 V/nA nA % of Span nA/V of Output ppm MV/°C p A /° C
4 5 0.999
+9 +12 1.001 ± 15 ± 0.02 ± 0.31 ± 20 ± 100
V V V/V mV % of Span mV/V ppm (PV or MV)/° C µV/°C dB dB dB dB nA % of Span µs ms µs µs mA mA mV µA V V µA V V V mA mA mA
CURRENT MEASURE HOLD MODE LEAKAGE CROSSTALK
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SETTLING TIMES TO 0.01% Voltage Force and Guard Voltage Current Force (200 µA Range) MEAS_OUT Pin SHORT CIRCUIT CURRENT LIMIT MAGNITUDE GUARD SCC LIMIT MAGNITUDE GUARD OFFSET (FROM SENSE INPUT PIN) IB (DAC1, DAC2) CURRENT DIGITAL INPUTS V IH V IL IIN (Input leakage current) POWER SUPPLIES VCC (Positive Analog Supply Voltage) VEE (Negative Analog Supply Voltage) VDD (Logic Supply Voltage) ICC (Positive Analog Supply Current) IEE (Negative Analog Supply Current) IDD (Logic Supply Current Is 0 with Inputs at Rails, Worst Case @ 2.4 V IN) NOTES
1 2
PV = Programmed Value, MV = Measured Value, FSR = Full-Scale Range = span. Output connected: DAC2 and 2 mA range selected, unconditionally. 3 f < 40 Hz, both channels in current force mode; other channel output voltage swinging rail to rail. Specifications subject to change without notice.
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AD53508
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
PIN FUNCTION DESCRIPTIONS Pin Name Description 2.5 V Reference Input First of Two Switchable Inputs Second of Two Switchable Inputs External RS and C Common External Capacitor External Resistor External Resistor Sense Input Force Output Guard Drive Output Measurement Output +15 V Analog Supply Connect Measure Output to Bus 10 V Analog Supply Force V (When Hi) or I (When Lo) Control Input Select DAC1 (When Lo) or DAC2 Control Input Control Input Select 2 mA Range (Active Lo) Select 200 µA Range (Active Lo) Measure Forced Voltage or Current Connect Pin Drive (Active Lo) Connect Pin Drive (Active Lo) Select 200 µA Range (Active Lo) Select 2 mA Range (Active Lo) Control Input Control Input Select DAC1 (When Lo) or DAC2 Control Input Force V (When Hi) or I (When Lo) Digital Ground Connect Measure Output to Bus +5 V Digital Supply Measurement Output Guard Drive Output Force Output Sense Input External Resistor External Resistor External Capacitor External RS and C Common Second of Two Switchable Inputs First of Two Switchable Inputs
Unit V V V V mW °C °C °C V Condition
Min VDD to VEE VCC to VEE VDD to DGND Digital Inputs to DGND Power Dissipation Operating Temperature Range Storage Temperature Lead Temperature Force/Sense Outputs 0.3 0.3 0.3 0.3
Max +26.4 +26.4 +6 VCC+0.3 700
TA +75°C
70 +125 +300 VEE0.8 VCC+0.8
25 60
Soldering (10 sec) Or 75 mA, Whichever Is Less
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD53508JP
Temperature Range 25°C to 70°C
Package Description Plastic Leaded Chip Carrier
Package Option P-44A
PIN CONFIGURATION
C1 A EXT RC A DAC1 A EXT RC B C1 B
6
5
4
3
2
1
44 43 42 41 40 PIN 1 IDENTIFIER
R2 A 7 SENSE A 8 FORCE A 9 GUARD A 10 MEAS OUT A 11 VCC 12 M CON A* 13 VEE 14 FORCE I A* 15 FORCE EN A* 16 DAC1 SEL A* 17
39 38 37 36
R2 B SENSE B FORCE B GUARD B MEAS OUT B
AD53508
TOP VIEW (Not to Scale)
35 34
VDD 33 M CON B* 32 DIGGND
31 30 29
FORCE I B* FORCE EN B* DAC1 SEL B*
18 19 20 21 22 23 24 25 26 27 28
* = ACTIVE LO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
DSR_2.5 DAC2_A DAC1_A EXT_RC_A C1_A R1_A R2_A SENSE_A FORCE_A GUARD_A MEAS_OUT_A VCC M_CON_A * VEE FORCE_I_A * FORCE_EN_A * DAC1_SEL_A * INTEG_A * HOLD_A * I_RANGE0_A * I_RANGE1_A * VERIFY* OUTPUT_CON_A * OUTPUT_CON_B * I_RANGE1_B * I_RANGE0_B * HOLD_B * INTEG_B * DAC1_SEL_B * FORCE_EN_B * FORCE_I_B * DIGGND M_CON_B * VDD MEAS_OUT_B GUARD_B FORCE_B SENSE_B R2_B R1_B C1_B EXT_RC_B DAC1_B DAC2_B
DAC2 A DSR 2.5
DAC2 B DAC1 B
R1 A
VERIFY* OUTPUT CON A*
INTEG A*
HOLD A* I RANGE0 A*
OUTPUT CON B*
I RANGE1 B*
I RANGE1 A*
I RANGE0 B* HOLD B*
INTEG B*
R1 B
* = Active Lo CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD53508 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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Table I. Data Table
Data Latch Bits S1 S2 S3 S4 S5 S6 S7 S9 S17 S8 S13, S10 S15, S14 S16 S11 S12 S18
Voltage Force/Current Measure Irange 0 On Off On On Irange 1 On Off On On Integrate Range On Off On On Integrate On Off On On Hold/Measure On Off On On Current Force/Voltage Measure Irange 0 On On Off Off Irange 1 On On Off Off Disable Mode: Output Connected X X X On Verify/Voltage Force On On Off Verify/Current Force On Off On Disconnect X X X On Off On X
Off Off Off Off Off
On On On On On
Off Off Off Off Off
Off Off Off Off On
Off Off Off Off On
On On On On Off
On On On Off Off
On Off Off Off Off
Off On Off Off Off
Off Off On On Off
Off Off On On On
On On On On On
On On Off Off On Off X
On On Off On On X Off
Off Off On Off Off X On
Off Off Off Off Off On X
Off Off Off Off Off Off X
On On On On On Off X
On On X On On On X
On Off On On On Off X
Off On Off Off Off Off X
Off Off Off Off Off Off X
Off Off Off Off Off On X
On On On On On Off X
DAC2 Select: Enabled X X X
CAPACITOR CHARGE
INTEGRATE* INTEGRATE HOLD* * = ACTIVE LO
DISCHARGE CAPACITOR HOLD
Figure 1. Integrate/Current Measure Timing Diagram
Table II. Truth Table
* = Active LO Control Input M_CON* VERIFY* FORCE_I* FORCE_EN* DAC1_SEL* INTEG* HOLD* I_RANGE0* I_RANGE1* OUTPUT_CON* DAC1 LO HI HI LO LO HI HI LO HI LO DAC2 LO HI HI LO HI HI HI LO HI LO DAC1 LO HI HI LO LO HI HI HI LO LO DAC2 LO HI HI LO HI HI HI HI LO LO FV/MI 2 mA FV/MI 200 mA FV/MI Integrate DAC1 Voltage Settle LO HI HI LO LO HI HI HI HI LO Integrate LO HI HI LO LO LO HI HI HI LO Hold LO HI HI LO LO LO LO HI HI LO FV/MI Integrate DAC 2 Voltage Settle LO HI HI LO HI HI HI HI HI LO Integrate LO HI HI LO HI LO HI HI HI LO Hold LO HI HI LO HI LO LO HI HI LO DA C 1 LO HI LO LO LO HI HI LO HI LO DA C 2 LO HI LO LO HI HI HI LO HI LO DAC1 LO HI LO LO LO HI HI HI LO LO DAC2 LO HI LO LO HI HI HI HI LO LO DAC1 LO LO HI LO LO HI HI X X LO DA C 2 LO LO HI LO HI HI HI X X LO DAC1 LO LO LO LO LO HI HI X X LO DA C 2 LO LO LO LO HI HI HI X X LO X X X X X X X X X HI FI/MV 2 mA FI/MV 200 µA FV/Verify FI/Verify Disconnect Disable Output Connected X X X HI X X X X X LO
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