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Details, datasheet, quote on part number:AD5443
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Datasheet text preview:
PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES +2.5 V to +5.5 V Supply Operation 50MHz Serial Interface 10MHz Multiplying Bandwidth ±10V Reference Input Extended Temperature Range -40 oC to +125 oC 10-Lead MSOP Package Pin Compatible 8, 10 and 12 Bit Current Output DACs Guaranteed Monotonic Four Quadrant Multiplication Power On Reset with Brown out Detec Daisy Chain Mode Readback Function 0.4µA typical Power Consumption APPLICATIONS Portable Battery Powered Applications Waveform Generators Analog Processing Instrumentation Applications Programmable Amplifiers and Attenuators Digitally-Controlled Calibration Programmable Filters and Oscillators Composite Video Ultrasound Gain, offset and Voltage Trimming
High Bandwidth CMOS 8/10/12-Bit Serial Interface Multiplying DACs AD5426/AD5432/AD5443*
F U N C T I O N A L BLOCK DIAGRAM
VDD
VREF R 8/10/12 BIT R-2R DAC RFB IOUT1 IOUT2
AD5426/ AD5432/ AD5443
DAC REGISTER Power On Reset
INPUT LATCH
SYNC SCLK SDIN
CONTROL LOGIC & INPUT SHIFT REGISTER
SDO
GND
G E N E R A L DESCRIPTION
The AD5426/AD5432/AD5443 are CMOS 8, 10 and 12-bit Current Output digital-to-analog converters respectively. These devices operate from a +2.5 V to 5.5 V power supply, making them suited to battery powered applications and many other applications. These DACs utilize double buffered 3-wire serial interface that is compatible with SPITM, QSPITM, MICROWIRETM and most DSP interface standards. In addition, a serial data out pin (SDO) allows for daisy chaining when multiple packages are used. Data readback allows the user to read the contents of the DAC register via the SDO pin. On power-up, the internal shift register and latches are filled with zeros and the DAC outputs are at zero scale. As a result of manufacture on a CMOS sub micron process, they offer excellent four quadrant multiplication
* U S Patent Number 5,689,257 SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation.
characteristics, with large signal multiplying bandwidths o f 10MHz. The applied external reference input voltage (VREF) determines the full scale output current. An integrated feedback resistor (RFB) provides temperature tracking and full scale voltage output when combined with an external Current to Voltage precision amplifier. The AD5426/AD5432/AD5443 DACs are available in s m a l l 10-lead MSOP packages.
P R O D U C T HIGHLIGHTS
1. 2. 3.
1 0 M H z Multiplying Bandwidth 3mm x 5mm 10-lead MSOP package Low Voltage, Low Power Current Output DACs.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P O. Box 9106, Norwood, MA 02062-9106, U.S.A. . Tel: 781/329-4700 World Wide Web Site: http://www.analog.com F a x : 781/326-8703 Analog Devices, Inc., 2003
PRELIMINARY TECHNICAL DATA
AD54V26/AD5432/AxDO5V.4All specifications TCItoFTICATIotherwise1noted. DC performance measured with 43SPE ONS (V = 2.5 to 5.5 V, V = +10 V, I = unless
DD REF OUT MIN MAX
OP1177, AC performance with AD9631 unless otherwise noted.)
Parameter
STATIC PERFORMANCE AD5426 Resolution Relative Accuracy Differential Nonlinearity AD5432 Resolution Relative Accuracy Differential Nonlinearity AD5443 Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Error Temp Coefficient2 Output Leakage Current Output Voltage Compliance Range REFERENCE INPUT Reference Input Range VREF Input Resistance DIGITAL INPUTS/OUTPUT Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current, IIL Input Capacitance VDD = 4.5 V to 5.5 V Output Low Voltage, VOL Output High Voltage, VOH VDD = 2.5 V to 3.6 V Output Low Voltage, VOL Output High Voltage, VOH DYNAMIC PERFORMANCE2 Reference Multiplying BW Output Voltage Settling Time AD5426 AD5432 AD5443 Slew Rate Digital to Analog Glitch Impulse Multiplying Feedthrough Error Output Capacitance Digital Feedthrough Total Harmonic Distortion Output Noise Spectral Density SFDR performance I n t e r m o d u l a t i o n Distortion POWER REQUIREMENTS Power Supply Range IDD P o w e r Supply Sensitivity 2 2.5 0.4
2 2
Min
Typ
Max
Units
Conditions
8 ±0.5 ±1 10 ±1 ±1 12 ±2 ±1 ±2 ±5 ±10 ±50 TBD ±10 10
Bits LSB LSB Bits LSB LSB
Guaranteed Monotonic
Guaranteed Monotonic
Bits LSB LSB Guaranteed Monotonic mV ppm FSR/°C nA Data = 0000H, TA = 25°C, I OUT1 nA Data = 0000H, IOUT1 V V k V V V µA pF V V V V MHz MHz
8 1.7
12
Input resistance TC = -50ppm/°C VDD = 2.5 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2.5 V to 2.7 V
0.8 0.7 1 10 0.4 V DD - 1 0.4 VDD - 0.5 10 TBD 30 35 40 100 3 TBD TBD TBD
ISINK = 200 µA ISOURCE = 200 µA ISINK = 200 µA ISOURCE = 200 µA VREF = 100 mV rms, DAC loaded all 1s VREF = 6 V rms, DAC loaded all 1s Measured to ½ LSB. RLOAD = 100, CLOAD = 15pF. DAC latch alternately loaded with 0s and 1s.
-75 2 4 5 -85 -85 25 72 TBD 5.5 10 0.001
ns ns ns V/µs nV-s dB pF pF nV-s dB dB n V / H z dB dB V µA %/%
1 LSB change around Major Carry DAC latch loaded with all 0s. Reference = 10kHz. DAC Latches Loaded with all 0s DAC Latches Loaded with all 1s Feedthrough to DAC output with SYNC high and Alternate Loading of all 0s and all 1s. VREF = 6 V rms, All 1s loaded, f = 1kHz VREF = 5 V, Sinewave generated from digital code. @ 1kHz
Logic Inputs = 0 V or VDD VDD = ±5%
NOTES 1 T e m p e r a t u r e range is as follows: Y Version: 40°C to +125°C. 2 Guaranteed by design and characterisation, not subject to production test. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA Single Supply Operation (Biased Mode) AD5426/AD5432/AD5443
(VDD = 2.5 V to 5.5 V, VREF = + 2V, IOUT2 = +1 V. All specifications TMIN to TMAX unless otherwise noted. DC performance measured with OP1177, AC performance with AD9631 unless otherwise noted.)
Parameter
STATIC PERFORMANCE AD5426 Resolution Relative Accuracy Differential Nonlinearity AD5432 Resolution Relative Accuracy Differential Nonlinearity AD5443 Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Error Temp Coefficient2 Output Leakage Current Output Voltage Compliance Range REFERENCE INPUT Reference Input Range VREF Input Resistance DIGITAL INPUTS/OUTPUT Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current, IIL Input Capacitance VDD = 4.5 V to 5.5 V Output Low Voltage, VOL Output High Voltage, VOH VDD = 2.5 V to 3.6 V Output Low Voltage, VOL Output High Voltage, VOH DYNAMIC PERFORMANCE2 Reference Multiplying BW Output Voltage Settling Time AD5426 AD5432 AD5443 Slew Rate Digital to Analog Glitch Impulse Multiplying Feedthrough Error Output Capacitance Digital Feedthrough Total Harmonic Distortion Output Noise Spectral Density SFDR performance I n t e r m o d u l a t i o n Distortion POWER REQUIREMENTS Power Supply Range IDD P o w e r Supply Sensitivity 2 2.5 0.4
2 2
Min
Typ
Max
Units
Conditions
8 ±0.5 ±1 10 ±1 ±1 12 ±2 ±1 ±2 ±5 ±10 ±50 TBD tbd 10
Bits LSB LSB Bits LSB LSB
Guaranteed Monotonic
Guaranteed Monotonic
Bits LSB LSB Guaranteed Monotonic mV ppm FSR/°C nA Data = 0000H, TA = 25°C, IOUT1 nA Data = 0000H, IOUT1 V V k V V V µA pF V V V V MHz MHz
8 1.7
12
Input resistance TC = -50ppm/°C VDD = 2.5 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2.5 V to 2.7 V
0.8 0.7 1 10 0.4 V DD - 1 0.4 VDD - 0.5 10 TBD 30 35 40 100 3 TBD TBD TBD
ISINK = 200 µA ISOURCE = 200 µA ISINK = 200 µA ISOURCE = 200 µA VREF = 100 mV rms, DAC loaded all 1s VREF = 1 V, DAC loaded all 1s Measured to ½ LSB. RLOAD = 100, CLOAD = 15pF. VREF = 0V,DAC latch alternately loaded with 0s & 1s.
-75 2 4 5 -85 -85 25 72 TBD 5.5 10 0.001
ns ns ns V/µs nV-s dB pF pF nV-s dB dB n V /H z dB dB V µA %/%
1 LSB change around Major Carry DAC latch loaded with all 0s. Reference = 10kHz. DAC Latches Loaded with all 0s DAC Latches Loaded with all 1s Feedthrough to DAC output with SYNC high and Alternate Loading of all 0s and all 1s. VREF = 2 Vp-p, 1V Bias, All 1s loaded, f = 1kHz VREF = 2 V, Sinewave generated from digital code. @ 1kHz
Logic Inputs = 0 V or VDD VDD = ±5%
NOTES 1 T e m p e r a t u r e range is as follows: Y Version: 40°C to +125°C. 2 Guaranteed by design and characterisation, not subject to production test. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA
AD5426/AD5432/AD5443SPECIFICATIONS1 V to 5.5 TIMING CHARACTERISTICS1 o(Vther=w2.5e noted.) V, V = +5 V, I 2 = O V. All specifications T is
DD REF OUT
MIN
to TMAX unless
Parameter fSCLK t1 t2 t3 t42 t5 t6 t7 t8 t93
Limit at TMIN, TMAX 50 20 8 8 13 5 4.5 5 30 25
Units M H z max ns min ns min ns min ns min ns min ns min ns min ns min ns min
Conditions/Comments Max Clock frequency SCLK Cycle time S C L K High Time SCLK Low Time SYNC falling edge to SCLK active edge setup time Data Setup Time Data Hold Time SYNC rising edge to SCLK active edge M i n i m u m SYNC high time SCLK Active edge to SDO valid
NOTES 1 See Figures 1 & 2. Temperature range is as follows: B Version: 40°C to +105°C. Guaranteed by design and characterisation, not subject to production test. All input signals are specified with tr =tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 2 Falling or Rising edge as determined by control bits of Serial word. 3 Daisychain and Readback modes cannot operate at max clock frequency. SDO timing specifications measured with load circuit as shown in Figure 3. Specifications subject to change without notice.
t1 SCLK t2 t8 t4 SYNC t6 t5 DIN DB15 DB0 t3 t7
ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. TIMING AS PER ABOVE, WITH SCLK INVERTED.
Figure 1. Stand Alone Mode Timing Diagram.
t1 SCLK t2 t4 SYNC t6 t3 t7
t8
t5 SDIN DB15 (N)
DB0 (N) t9
DB15 (N+1)
DB0 (N+1)
SDO
DB15(N)
DB0(N)
ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS PER ABOVE, WITH SCLK INVERTED.
Figure 2. Daisy Chain and Readback Modes Timing Diagram
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PRELIMINARY TECHNICAL DATA AD5426/AD5432/AD5443
ABSOLUTE MAXIMUM RATINGS1,
(TA = +25°C unless otherwise noted)
2
VDD to GND 0.3 V to +7 V VREF, RFB to GND 12 V to +12 V IOUT1, IOUT2 to GND 0.3 V to +7 V ±10 mA Input Current to any pin except supplies Logic Inputs & Output3 -0.3V to VDD +0.3 V O p e r a t i n g Temperature Range Extended Industrial (Y Version) 40°C to +125°C Storage Temperature Range 65°C to +150°C J u n c t i o n Temperature +150°C 206°C/W 10 lead MSOP JA Thermal Impedance L e a d Temperature, Soldering (10seconds) 300°C IR Reflow, Peak Temperature (<20 seconds) +235°C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Transient currents of up to 100mA will not cause SCR latchup. 3 Overvoltages at SCLK, SYNC, DIN, will be clamped by internal diodes. Current should be limited to the maximum ratings given.
200uA TO OUTPUT PIN
IOL VOH (MIN) + VOL (MAX)
CL 50pF 200uA IOH
2
Figure 3. Load Circuit for SDO Timing Specifications
O R D E R I N G GUIDE
Model AD5426YRM AD5432YRM AD5443YRM
Resolution INL (LSBs) Temperature Range Package Description Branding Package Option 8 10 12
±0.5 ±1 ±2
-40 oC to +125 oC -40 oC to +125 oC -40 oC to +125 oC
MSOP MSOP MSOP
D01 D02 D03
RM-10 RM-10 RM-10
CAUTION E S D (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily a c c u m u l a t e on the human body and test equipment and can discharge without detection. Although the AD5426/AD5432/AD5443 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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