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Details, datasheet, quote on part number:AD5445YRU
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Datasheet text preview:
PRELIMINARY TECHNICAL DATA
a
High Bandwidth CMOS 8-/10-/12-Bit Parallel Interface Multiplying DACs AD5424/AD5433/AD5445* Preliminary Technical Data
F U N C T I O N A L BLOCK DIAGRAM
VDD AD5424/ AD5433/ AD5445 VREF R 8/10/12 BIT R-2R DAC RFB IOUT1 IOUT2
FEATURES +2.5 V to +5.5 V Supply Operation Fast Parallel Interface (10ns WR cycle) WR 10MHz Multiplying Bandwidth ±10V Reference Input Extended Temperature Range -40 oC to +125 oC 20-Lead TSSOP and Chip Scale (4 x4mm) Packages 8, 10 and 12 Bit Current Output DACs Pin compatible 8, 10 & 12 Bit DACs in Chip Scale Guaranteed Monotonic Four Quadrant Multiplication Power On Reset with Brown out detect Readback Function 0.4µA typical Power Consumption APPLICATIONS Portable Battery Powered Applications Waveform Generators Analog Processing Instrumentation Applications Programmable Amplifiers and Attenuators Digitally-Controlled Calibration Programmable Filters and Oscillators Composite Video Ultrasound Gain, offset and Voltage Trimming
Power On Reset
DAC REGISTER
CS R/W
INPUT LATCH
GND
DB0
DB7/DB9/DB11
DATA INPUTS
G E N E R A L DESCRIPTION
The AD5424/AD5433/AD5445 are CMOS 8, 10 and 12-bit current output digital-to-analog converters (DACs) respectively. These devices operate from a +2.5 V to 5.5 V power supply, making them suited to battery powered applications and many other applications. These DACs utilize Data readback allowing the user to read the contents of the DAC register via the DB pins. On power-up, the internal register and latches are filled with zeros and the DAC outputs are at zero scale. As a result of manufacture on a CMOS sub micron process, they offer excellent four quadrant multiplication characteristics, with large signal multiplying bandwidths of up to 10MHz.
The applied external reference input voltage (VREF) determines the full scale output current. An integrated feedback resistor (RFB) provides temperature tracking and full scale voltage output when combined with an external I - t o V precision amplifier. The AD5424 is available in small 20 lead CSP and 16 lead TSSOP packages, while the AD5433/AD5445 DACs are available in small 20-lead CSP and TSSOP packages.
P R O D U C T HIGHLIGHTS
1. 2. 3.
1 0 M H z Multiplying Bandwidth 4mm x 4mm Chip Scale Packages and small T S S O P packages. Low Voltage, Low Power Current Output DACs.
* U S Patent Number 5,689,257
REV. PrJ May 2003
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P O. Box 9106, Norwood, MA 02062-9106, U.S.A. . Tel: 781/329-4700 World Wide Web Site: http://www.analog.com F a x : 781/326-8703 Analog Devices, Inc., 2003
PRELIMINARY TECHNICAL DATA
AD54V24/AD5433/A2D5V.4All specifications TCIto TICunlessIotherwise1noted. DC performance measured with 45SPE F AT ONS (V = 2.5 to 5.5 V, V = +10 V, I =O
DD REF OUT MIN MAX
OP1177, AC performance with AD9631 unless otherwise noted.)
Parameter STATIC PERFORMANCE AD5424 Resolution Relative Accuracy Differential Nonlinearity AD5433 Resolution Relative Accuracy Differential Nonlinearity AD5445 Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Error Temp Coefficient2 Output Leakage Current Output Voltage Compliance Range REFERENCE INPUT Reference Input Range VREF Input Resistance DIGITAL INPUTS/OUTPUT2 Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current, IIL Input Capacitance VDD = 4.5 V to 5.5 V Output Low Voltage, VOL Output High Voltage, VOH VDD = 2.5 V to 3.6 V Output Low Voltage, VOL Output High Voltage, VOH DYNAMIC PERFORMANCE2 Reference Multiplying BW Output Voltage Settling Time AD5424 AD5433 AD5445 Slew Rate Digital to Analog Glitch Impulse Multiplying Feedthrough Error Output Capacitance Digital Feedthrough Total Harmonic Distortion Output Noise Spectral Density SFDR performance I n t e r m o d u l a t i o n Distortion POWER REQUIREMENTS Power Supply Range IDD P o w e r Supply Sensitivity 2 2.5 0.4 5 -85 -85 25 72 TBD 5.5 10 0.001
2
Min
Typ
Max
Units
Conditions
8 ±0.5 ±1 10 ±1 ±1 12 ±2 ±1 ±2 ±5 ±10 ±50 TBD ±10 10
Bits LSB LSB Bits LSB LSB
Guaranteed Monotonic
Guaranteed Monotonic
Bits LSB LSB Guaranteed Monotonic mV ppm FSR/°C nA Data = 0000H, TA = 25°C, IOUT1 nA Data = 0000H, IOUT1 V V k V V V µA pF V V V V MHz MHz
8 1.7
12
Input resistance TC = -50ppm/°C VDD = 2.5 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2.5 V to 2.7 V
0.8 0.7 1 10 0.4 V DD - 1 0.4 VDD - 0.5 10 TBD 30 35 40 100 3 TBD TBD TBD
ISINK = 200 µA ISOURCE = 200 µA ISINK = 200 µA ISOURCE = 200 µA VREF = 100 mV rms, DAC loaded all 1s VREF = 6 V rms, DAC loaded all 1s Measured to ½ LSB. RLOAD = 100, CLOAD = 15pF. DAC latch alternately loaded with 0s and 1s. 1 LSB change around Major Carry DAC latch loaded with all 0s. Reference = 10kHz. DAC Latches Loaded with all 0s DAC Latches Loaded with all 1s Feedthrough to DAC output with CS high and Alternate Loading of all 0s and all 1s. VREF = 6 V rms, All 1s loaded, f = 1kHz VREF = 5 V, Sinewave generated from digital code. @ 1kHz
-75 2 4
ns ns ns V/µs nV-s dB pF pF nV-s dB dB n V /H z dB dB V µA %/%
Logic Inputs = 0 V or VDD VDD = ±5%
NOTES 1 T e m p e r a t u r e range is as follows: Y Version: 40°C to +125°C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA Single Supply Operation (Biased Mode) AD5424/AD5433/AD5445
(VDD = 2.5 V to 5.5 V, VREF = +2 V, IOUT2 = 1 V. All specifications TMIN to TMAX unless otherwise noted. DC performance measured with OP1177, AC performance with AD9631 unless otherwise noted.)
Parameter STATIC PERFORMANCE AD5424 Resolution Relative Accuracy Differential Nonlinearity AD5433 Resolution Relative Accuracy Differential Nonlinearity AD5445 Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Error Temp Coefficient2 Output Leakage Current Output Voltage Compliance Range REFERENCE INPUT Reference Input Range VREF Input Resistance DIGITAL INPUTS/OUTPUT2 Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current, IIL Input Capacitance VDD = 4.5 V to 5.5 V Output Low Voltage, VOL Output High Voltage, VOH VDD = 2.5 V to 3.6 V Output Low Voltage, VOL Output High Voltage, VOH DYNAMIC PERFORMANCE2 Reference Multiplying BW Output Voltage Settling Time AD5424 AD5433 AD5445 Slew Rate Digital to Analog Glitch Impulse Multiplying Feedthrough Error Output Capacitance Digital Feedthrough Total Harmonic Distortion Output Noise Spectral Density SFDR performance I n t e r m o d u l a t i o n Distortion POWER REQUIREMENTS Power Supply Range IDD P o w e r Supply Sensitivity 2 2.5 0.4 5 -85 -85 25 72 TBD 5.5 10 0.001
2
Min
Typ
Max
Units
Conditions
8 ±0.5 ±1 10 ±1 ±1 12 ±2 ±1 ±2 ±5 ±10 ±50 TBD tbd 10
Bits LSB LSB Bits LSB LSB
Guaranteed Monotonic
Guaranteed Monotonic
Bits LSB LSB Guaranteed Monotonic mV ppm FSR/°C nA Data = 0000H, TA = 25°C, I OUT1 nA Data = 0000H, IOUT1 V V k V V V µA pF V V V V MHz MHz
8 1.7
12
Input resistance TC = -50ppm/°C VDD = 2.5 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2.5 V to 2.7 V
0.8 0.7 1 10 0.4 V DD - 1 0.4 VDD - 0.5 10 TBD 30 35 40 100 3 TBD TBD TBD
ISINK = 200 µA ISOURCE = 200 µA ISINK = 200 µA ISOURCE = 200 µA VREF = 100 mV rms, DAC loaded all 1s VREF = 1 V rms, DAC loaded all 1s Measured to ½ LSB. RLOAD = 100, CLOAD = 15pF. DAC latch alternately loaded with 0s and 1s. 1 LSB change around Major Carry DAC latch loaded with all 0s. Reference = 10kHz. DAC Latches Loaded with all 0s DAC Latches Loaded with all 1s Feedthrough to DAC output with CS high and Alternate Loading of all 0s and all 1s. VREF = 2 Vp-p, 1V Bias, All 1s loaded, f = 1kHz VREF = 2 V, Sinewave generated from digital code. @ 1kHz
-75 2 4
ns ns ns V/µs nV-s dB pF pF nV-s dB dB n V / H z dB dB V µA %/%
Logic Inputs = 0 V or VDD VDD = ±5%
NOTES 1 T e m p e r a t u r e range is as follows: Y Version: 40°C to +125°C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
REV. PrJ
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PRELIMINARY TECHNICAL DATA
AD5424/AD5433/AD5445SPECIFICATIONS1 V to 5.5 TIMING CHARACTERISTICS1,2 (oVther=w2.5 noted.) V, V = +5 V, I ise
DD REF
O U T2
= O V. All specifications TMIN to TMAX unless
Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9
Limit at TMIN, TMAX 0 0 10 6 0 5 7 5 25 5 10
Units ns ns ns ns ns ns ns ns ns ns ns min min min min min min min typ max typ max
Conditions/Comments R/W to CS Setup Time R/W to CS Hold Time CS Low Time (Write Cycle) Data Setup Time Data Hold Time R/W high to CS low CS Min High Time Data Acess Time Bus Relinquish Time
NOTES 1 See Figure 1. Temperature range is as follows: B Version: 40°C to +105°C. Guaranteed by design and characterisation, not subject to production test. 2 All input signals are specified with tr =tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Digital Output timing measured with Load circuit in Figure 2. Specifications subject to change without notice.
R/W
t1
t2
t6
t2
t7
CS
t3 t4 t5 t8
DATA VALID
t9
DATA
DATA VALID
Figure 1. Timing Diagram.
200uA TO OUTPUT PIN
IOL VOH (MIN) + VOL (MAX)
CL 50pF 200uA IOH
2
Figure 2. Load Circuit for Data Output Timing Specifications
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PRELIMINARY TECHNICAL DATA AD5424/AD5433/AD5445
A B S O L U T E MAXIMUM RATINGS 1
(TA = +25°C unless otherwise noted)
VDD to GND 0.3 V to +7 V VREF, RFB to GND 12 V to +12 V IOUT1, IOUT2 to GND 0.3 V to +7 V -0.3V to VDD +0.3 V Logic Inputs & Output2 O p e r a t i n g Temperature Range Extended Industrial (Y Version) 40°C to +125°C Storage Temperature Range 65°C to +150°C J u n c t i o n Temperature +150°C 16 lead TSSOP JA Thermal Impedance 150°C/W 143°C/W 20 lead TSSOP JA Thermal Impedance 20 lead CSP JA Thermal Impedance 135°C/W L e a d Temperature, Soldering (10seconds) 300°C IR Reflow, Peak Temperature (< 20 seconds) +235°C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at DBx, CS and W/R, will be clamped by internal diodes. Current should be limited to the maximum ratings given.
O R D E R I N G GUIDE
Model AD5424YRU AD5424YCP AD5433YRU AD5433YCP AD5445YRU AD5445YCP Resolution 8 8 10 10 12 12 INL (LSBs) ±0.5 ±0.5 ±1 ±1 ±2 ±2 Temperature Range -40 -40 -40 -40 -40 -40
o o
Package Description TSSOP (Thin Shrink Small Outline Package) C S P (Chip Scale Package) TSSOP (Thin Shrink Small Outline Package) C S P (Chip Scale Package) TSSOP (Thin Shrink Small Outline Package) C S P (Chip Scale Package)
Package Option RU-16 CP-20 RU-20 CP-20 RU-20 CP-20
C C o C o C o C o C
to to to to to to
+125 +125 +125 +125 +125 +125
o o
C C o C o C o C o C
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily a c c u m u l a t e on the human body and test equipment and can discharge without detection. Although the AD5424/AD5433/AD5445 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. PrJ
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