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Details, datasheet, quote on part number:AD5450YUJ-REEL
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| Part: | AD5450YUJ-REEL |
| Category: | Data Conversion => DAC (Digital to Analog Converters) => <10 bit => 8 bit |
| Description: | 8-Bit High Bandwidth Multiplying DACs With Serial Interface.<<<>>>the AD5450 is a CMOS 8-bit Current Output Digital-to-analog Converter. This Device Operates From a +2.5 V to 5.5 V Power Supply, Making it Suited to Battery Powered Applications And Many Other Applications.<<<>>><<<>>>features <<<>>><<<>>>+2.5 V to +5.5 V Supply Operation <<<>>>50 MHZ Serial Interface <<<>>>10 MHZ Multiplying Bandwidth <<<>>> 10 V Reference Input <<<>>>8-Lead Tsot & Msop Packages <<<>>>Pin Compatible 8, 10, 12 And 14 Bit Current Output DACs <<<>>>Extended Temperature Range 40 C to +125 C <<<>>>Guaranteed Monotonic <<<>>>Four Quadrant Multiplication <<<>>>Power on Reset With Brown Out Detect <<<>>><5 a Typical Current Consumption |
| Company: | Analog Devices |
| Datasheet: | Download AD5450YUJ-REEL datasheet File size : 129 kB |
| Request For quote: | Find where to buy AD5450YUJ-REEL
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Datasheet text preview:
PRELIMINARY TECHNICAL DATA
a
8/10/12/14-Bit High Bandwidth Multiplying DACs with Serial Interface Preliminary Technical Data AD5450/AD5451/AD5452/AD5453*
F U N C T I O N A L BLOCK DIAGRAM
VDD
FEATURES +2.5 V to +5.5 V Supply Operation 50MHz Serial Interface 10MHz Multiplying Bandwidth ±10V Reference Input 8-Lead TSOT & MSOP Packages Pin Compatible 8, 10, 12 and 14 Bit Current Output DACs Extended Temperature range 40°C to +125°C Guaranteed Monotonic Four Quadrant Multiplication Power On Reset with brown out detect <5µA typical Current Consumption APPLICATIONS Portable Battery Powered Applications Waveform Generators Analog Processing Instrumentation Applications Programmable Amplifiers and Attenuators Digitally-Controlled Calibration Programmable Filters and Oscillators Composite Video Ultrasound Gain, offset and Voltage Trimming
SYNC SCLK SDIN
VREF
R
8/10/12/14 BIT R-2R DAC
RFB IOUT1
AD5450/ AD5451/ AD5452/ AD5453
DAC REGISTER
Power On Reset
INPUT LATCH
CONTROL LOGIC & INPUT SHIFT REGISTER
GND
G E N E R A L DESCRIPTION
T h e AD5450/AD5451/AD5452/AD5453 are CMOS 8, 10, 12 and 14-bit Current Output digital-to-analog c o n v e r t e r s respectively. These devices operate from a +2.5 V to 5.5 V power supply, making them suited to battery powered applications and many other applications. These DACs utilize double buffered 3-wire serial interface that is compatible with SPITM, QSPITM, MICROWIRETM and most DSP interface standards. On power-up, the internal shift register and latches are filled with zeros and the DAC output is at zero scale. As a result of manufacture on a CMOS sub micron process, they offer excellent four quadrant multiplication characteristics, with large signal multiplying bandwidths o f 10MHz.
The applied external reference input voltage (VREF) determines the full scale output current. An integrated feedback resistor (RFB) provides temperature tracking and full scale voltage output when combined with an external Current to Voltage precision amplifier. T h e AD5450/AD5451/AD5452/AD5453 DACs are available in small 8-lead TSOT & MSOP packages.
* U S Patent Number 5,689,257 SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation.
REV. PrD Oct, 2003
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P O. Box 9106, Norwood, MA 02062-9106, U.S.A. . Tel: 781/329-4700 World Wide Web Site: http://www.analog.com F a x : 781/326-8703 Analog Devices, Inc., 2003
PRELIMINARY TECHNICAL DATA
AD54V50/AD5451/AxDO V.4All specifications453TSPEotherwiseCATIONS1 measured with 5 52/AD5 T to unless CIFI noted. DC performance (V = 2.5 to 5.5 V, V = +10 V, I =
DD REF OUT MIN MAX
OP1177, AC performance with AD9631 unless otherwise noted.)
Parameter S T A T I C PERFORMANCE AD5450 Resolution R e l a t i v e Accuracy D i f f e r e n t i a l Nonlinearity AD5451 Resolution R e l a t i v e Accuracy D i f f e r e n t i a l Nonlinearity AD5452 Resolution R e l a t i v e Accuracy D i f f e r e n t i a l Nonlinearity AD5453 Resolution R e l a t i v e Accuracy D i f f e r e n t i a l Nonlinearity T o t a l Unadjusted Error G a i n Error G a i n Error Temp Coefficient 2 O u t p u t Leakage Current Output Voltage Compliance Range R E F E R E N C E INPUT R e f e r e n c e Input Range V REF Input Resistance D I G I T A L INPUTS I n p u t High Voltage, V I H I n p u t Low Voltage, V IL I n p u t Leakage Current, I IL I n p u t Capacitance DYNAMIC PERFORMANCE 2
2 2
Min
Typ
Max
Units
Conditions
8 ±0.25 ±½ 10 ±0.25 ±½ 12 ±0.5 ±½ 14 ±2 ±1 ±2.44 ±1.22 ±5 ±10 ±50 1.23 ±10 9.3
Bits LSB LSB Bits LSB LSB Bits LSB LSB
G u a r a n t e e d Monotonic
G u a r a n t e e d Monotonic
G u a r a n t e e d Monotonic
Bits LSB LSB G u a r a n t e e d Monotonic mV mV ppm FSR/°C nA Data = 0000H, TA = 25°C, IOUT1 nA Data = 0000H, IOUT1 V V k V V V V µA pF
8 2.0 1.7
12
I n p u t resistance TC = -50ppm/°C V DD V DD V DD V DD = = = = 3.6 2.5 2.7 2.5 V V V V to to to to 5V 3.6 V 5.5 V 2.7 V
0.8 0.7 1 10
Reference Multiplying BW Output Voltage Settling Time
AD5450 AD5451 AD5452 AD5453 D i g i t a l Delay 1 0 % to 90% Dettling Time Digital to Analog Glitch Impulse M u l t i p l y i n g Feedthrough Error
10
MHz
100 110 160 180 20 10 3 -75
40 30
ns ns ns ns ns ns nV-s dB
VREF = +/-3.5V, DAC loaded all 1s VREF = 10V, RLOAD = 100, CLOAD = 15pF DAC latch alternately loaded with 0s and 1s. Measured to +/-16mV of FS Measured to +/-4mV of FS Measured to +/-1mV of FS Measured to +/-1mV of FS
I n t e r f a c e delay time Rise and Fall time, VREF = 10V, RLOAD = 1 0 0, CLOAD = 15pF 1 LSB change around Major Carry, V REF= 0 V D A C latch loaded with all 0s. R e f e r e n c e = 1MHz. R e f e r e n c e = 10MHz. D A C Latches Loaded with all 0s D A C Latches Loaded with all 1s D A C Latches Loaded with all 0s D A C Latches Loaded with all 1s F e e d t h r o u g h to DAC output with CS high and Alternate Loading of all 0s and all 1s.
O u t p u t Capacitance IOUT1 IOUT2 D i g i t a l Feedthrough
5 10 10 5 0.1
pF pF pF pF nV-s
2
REV. PrD
PRELIMINARY TECHNICAL DATA AD5450/AD5451/AD5452/AD5453
(VDD = 2.5 V to 5.5 V, VREF = +10 V, IOUTx = O V. All specifications TMIN to TMAX unless otherwise noted. DC performance measured with OP1177, AC performance with AD9631 unless otherwise noted.)
Parameter T o t a l Harmonic Distortion D i g i t a l THD, Clock = 1MHz 50kHz fOUT O u t p u t Noise Spectral Density S F D R performance (Wideband) U p d a t e = 1MHz 50kHz Fout 20kHz Fout S F D R performance (NarrowBand) 50kHz Fout 20kHz Fout I n t e r m o d u l a t i o n Distortion P O W E R REQUIREMENTS P o w e r Supply Range I DD P o w e r Supply Sensitivity 2 Min Typ -80 75 25 Max Units dB dB nV/Hz Conditions VREF = 3.5 V pk-pk, All 1s loaded, f = 1kHz
@ 1kHz U p d a t e = 1MHz, V REF = 3.5V
78 78 87 87 78
dB dB U p d a t e = 1MHz, V REF = 3.5V dB dB dB
f 1 = 20kHz, f2 = 25kHz, Update=1MHz, V REF= 3 . 5 V
2.5
5.5 1 0.001
V µA %/%
Logic Inputs = 0 V or VDD = ±5%
V DD
NOTES 1 T e m p e r a t u r e range is as follows: Y Version: 40°C to +125°C. 2 Guaranteed by design and characterisation, not subject to production test. S p e c i f i c a t i o n s subject to change without notice.
TIMING CHARACTERISTICS1(V
Parameter f SCLK t1 t2 t3 t4 t5 t6 t7 t8 VDD = 4.5 V to 5.5 V 50 20 8 8 8 5 4.5 5 30
REF
= +5 V, IOUT2 = O V. All specifications TMIN to TMAX unless otherwise noted.)
Conditions/Comments Max Clock frequency SCLK Cycle time S C L K High Time SCLK Low Time SYNC falling edge to SCLK active edge setup time Data Setup Time Data Hold Time SYNC rising edge to SCLK active edge M i n i m u m SYNC high time M H z max ns min ns min ns min ns min ns min ns min ns min ns min
VDD = 2.5 V to 5.5 V Units
NOTES 1 S e e Figures 1. Temperature range is as follows: Y Version: 40°C to +125°C. Guaranteed by design and characterisation, not subject to p r o d u c t i o n test. All input signals are specified with tr =tf = 5ns (10% to 90% of VDD ) and timed from a voltage level of (V IL + V IH) / 2 . Specifications subject to change without notice.
t1 SCLK t2 t8 t4 SYNC t6 t5 DIN DB15 DB0 t3 t7
Figure 1. Timing Diagram.
REV. PrD
3
PRELIMINARY TECHNICAL DATA AD5450/AD5451/AD5452/AD5453
ABSOLUTE MAXIMUM RATINGS1,
(TA = +25°C unless otherwise noted)
2
VDD to GND 0.3 V to +7 V VREF, RFB to GND 12 V to +12 V IOUT1 to GND 0.3 V to +7 V ±10 mA Input Current to any pin except supplies Logic Inputs & Output3 -0.3V to VDD +0.3 V O p e r a t i n g Temperature Range Industrial (Y Version) 40°C to +125°C Storage Temperature Range 65°C to +150°C J u n c t i o n Temperature +150°C 206°C/W 8 lead MSOP JA Thermal Impedance 8 lead TSOT JA Thermal Impedance 211°C/W L e a d Temperature, Soldering (10seconds) 300°C IR Reflow, Peak Temperature (<20 seconds) +235°C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Transient currents of up to 100mA will not cause SCR latchup. 3 Overvoltages at SCLK, SYNC, DIN, will be clamped by internal diodes. Current should be limited to the maximum ratings given.
O R D E R I N G GUIDE
Model AD5450YUJ AD5451YUJ AD5452YUJ AD5452YRM AD5453YUJ AD5453YRM
Resolution 8 10 12 12 14 14
INL
±0.25 ±0.25 ±0.5 ±0.5 ±2 ±2
Temperature Range -40 -40 -40 -40 -40 -40
o o
Package Description Branding TSOT TSOT TSOT MSOP TSOT MSOP
Package Option UJ-8 UJ-8 UJ-8 RM-8 UJ-8 RM-8
C C o C o C o C o C
to to to to to to
+125 +125 +125 +125 +125 +125
o o
C C o C o C o C o C
CAUTION E S D (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily a c c u m u l a t e on the human body and test equipment and can discharge without detection. Although the AD5450/AD5451/AD5452/AD5453 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
4
REV. PrD
PRELIMINARY TECHNICAL DATA AD5450/AD5451/AD5452/AD5453
P I N FUNCTION DESCRIPTION
MSOP 1 2 3
TSOT 8 7 6
Mnemonic Function I OUT1 GND SCLK DAC Current Output. Ground Pin. Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock input. Alternatively, by means of the serial control bits, the device may be configured such that data is clocked into the shift register on the rising edge of SCLK. Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By default, on power up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the user to change the active edge to rising edge. Active Low Control Input. This is the frame synchronization signal for the input data. Data is loaded to the shift register on the active edge of the f o l l o w i n g clocks. Positive power supply input. These parts can operate from a supply of +2.5 V to +5.5 V. DAC reference voltage input pin. DAC feedback resistor pin. Establish voltage output for the DAC by connecting to external amplifier output.
4
5
SDIN
5
4
SYNC
6 7 8
3 2 1
V DD VREF RFB
P I N CONFIGURATION TSOT (UJ-8)
AD5450/ AD5451/ VREF 2 AD5452/ AD5453 VDD 3 (Not to Scale) SYNC 4 RFB 1 8 IOUT1 7 GND 6 SCLK 5 SDIN
MSOP (RM-8)
IOUT1 1 AD5452/ AD5453 SCLK 3 (Not to Scale) GND 2 SDIN 4 8 RFB 7 VREF 6 VDD 5 SYNC
REV. PrD
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