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Part: AD5545
Category:
Description: Precision Dual 16-Bit DAC
Company: Analog Devices
Datasheet: Download AD5545 datasheet File size : 380 kB
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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES 16-bit Resolution AD5545 14-bit Resolution AD5555 ±2 LSB INL AD5545 ±1, ±1.5 LSB DNL AD5545 2mA Full Scale Current ± 20%, with VREF=10V 0.5µs Settling Time 2Q Multiplying Reference-input 4Hz BW 3-Wire Interface Compact TSSOP-16 Package APPLICATIONS Automatic Test Equipment Instrumentation Digitally Controlled Calibration Industrial Control PLCs
GENERAL DESCRIPTION The AD5545, 16-bit, current-output, digital-to-analog converter is designed to operate from a single +5 volt supply. The applied external reference input voltage VREF determines the full-scale output-current. An internal feedback resistor (RFB) provides temperature tracking for the full-scale output when combined with an external I to V precision amplifier. A serial-data interface offers high-speed, three-wire micro controller compatible inputs using serial-data-in (SDI), clock (CLK), and (CS). Additional LDAC function allows simultaneous update operation. The AD5545/AD5555 are packaged in the low profile compact TSSOP-16 package.
Dual, Current-Output Serial-Input, 16-/14-Bit DAC
AD5545/AD5555
VREFA VREFB
FUNCTIONAL DIAGRAMS
VDD
D0..D x
16 or 14
RFBA
INPUT REGISTER R DAC A REGISTER R DAC A
SDI
IOUTA AGNDA RFBB IOUTB AGNDB
CS CLK
EN DAC A B ADDR DECODE
INPUT REGISTER
R
DAC B REGISTER
R
DAC B
POW ER ON RESET
AD5545 AD5555
LDAC
DGNDF
RS MSB
ORDERING GUIDE
MODEL AD5545BRU AD5555CRU INL LSB ±2 ±1 DNL LSB ±1 ±1 RES (bits) 16 14 TEMP RANGE 40 / +85°C 40 / +85°C Package Description TSSOP-16 TSSOP-16 Package Option RU-16 RU-16
The AD5545 contains 3131 transistors. The die size measures xx mil X xx mil, xxxx sqmil.
REV. PrB, 18 FEB '2002 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 www.analog.com ©Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
AD5545/AD5555
ELECTRICAL CHARACTERISTICS at VDD = 5V±10% or VDD = 3V±10%, VSS = 0V, IOUT = Virtual GND, GND=0V, VREF = 10V, TA = Full
Operating temperature Range, unless otherwise noted. PARAMETER SYMBOL CONDITION STATIC PERFORMANCE1 Resolution N AD5545, 1 LSB = VREF/216 = 153µV when VREF = 10V Resolution N AD5555, 1 LSB = VREF/214 = 610µV when VREF = 10V Relative Accuracy INL AD5545 Grade: B Relative Accuracy INL AD5555 Grade: C Differential Nonlinearity DNL Monotonic Output Leakage Current IOUT Data = 0000H, TA = 25°C Output Leakage Current IOUT Data = 0000H, TA = TA MAX Full-Scale Gain Error GFSE Data = Full Scale Full-Scale Tempco2 TCVFS REFERENCE INPUT VREF Range VREF Input Resistance RREF Input Capacitance2 CREF ANALOG OUTPUT Output Current IOUT Data = Full Scale Output Capacitance2 COUT Code Dependent LOGIC INPUTS & OUTPUT Logic Input Low Voltage VIL Logic Input High Voltage VIH Input Leakage Current IIL Input Capacitance2 CIL 2, 3 INTERFACE TIMING Clock Input Frequency fCLK Clock Width High tCH Clock Width Low tCL CS to Clock Set Up tCSS Clock to CS Hold tCSH Data Setup t DS Data Hold tD H SUPPLY CHARACTERISTICS Power Supply Range VDD RANGE Positive Supply Current I DD Logic Inputs = 0V Power Dissipation PDISS Logic Inputs = 0V Power Supply Sensitivity PSS VDD = ±5% NOTES:
1. 2. 3. 4. All static performance tests (except IOUT) are performed in a closed loop system using an external precision OP1177 I-to-V converter amplifier. The AD5545 RFB terminal is tied to the amplifier output. Typical values represent average readings measured at 25°C These parameters are guaranteed by design and not subject to production testing. All input control signals are specified with tR = tF = 2.5ns (10% to 90% of +3V) and timed from a voltage level of 1.5V. All AC Characteristic tests are performed in a closed loop system using an OP42 I-to-V converter amplifier.
5V±10% 16 14 ±2 ±1 ±1 10 20 ±1/±4 1 -12/+12 5 5 2 200 0.8 2.4 10 10 40 10 10 0 10 5 10 4.5/5.5 10 0.055 0.006
UNITS Bits Bits LSB max LSB max LSB max nA max nA max
mV typ/max
ppm/°C typ V min/max k ohm typ4 pF typ mA typ pF typ V max V min µA max pF max MHz ns min ns min ns min ns min ns min ns min V min/max µA max mW max %/% max
-2-
18 FEB '2002, REV. PrB
PRELIMINARY TECHNICAL DATA
AD5545/AD5555
ELECTRICAL CHARACTERISTICS at VDD = 5V±10%, IOUT = Virtual GND, GND=0V, VREF = 10V,
TA = Full Operating Temperature Range, unless otherwise noted. PARAMETER AC CHARACTERISTICS Output Voltage Settling Time Reference Multiplying BW DAC Glitch Impulse Feed Through Error Digital Feed Through Total Harmonic Distortion Output Spot Noise Voltage NOTES:
1. 2. 3. 4.
SYMBOL tS BW Q VOUT/VREF Q THD eN
CONDITION To ±0.1% of Full Scale, Data = Zero Scale to Full Scale to Zero Scale VREF = 5VP-P, Data = Full Scale VREF = 0V, Data Zero Scale to Mid Scale to Zero Scale Data = Zero Scale, VREF = 100mVrms, same channel CS = 1, and fCLK = 1MHz VREF = 5VP-P, Data = Full Scale, f=1KHz f = 1kHz, BW = 1Hz
5V±10%
UNITS
0.5 4 7 -65 7 73 4
µs typ MHz typ nV-s typ dB nV-s typ dB typ nV/ rt Hz
All static performance tests (except IOUT) are performed in a closed loop system using an external precision OP177 I-to-V converter amplifier. The AD5545 RFB terminal is tied to the amplifier output. Typical values represent average readings measured at 25°C These parameters are guaranteed by design and not subject to production testing. All input control signals are specified with tR = tF = 2.5ns (10% to 90% of +3V) and timed from a voltage level of 1.5V. All AC Characteristic tests are performed in a closed loop system using an OP42 I-to-V converter amplifier.
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..... 0.3V, +8V VREF to GND ......18V, 18V Logic Inputs to GND....... 0.3V, +8V V(IOUT) to GND .......... 0.3V, VDD + 0.3V Input Current to Any Pin except Supplies...... ±50mA Package Power Dissipation ........... (TJ MAX TA)/ THETAJA Thermal Resistance THETAJA 16-lead TSSOP........ 150°C/W Maximum Junction Temperature (TJ MAX) ...... 150°C Operating Temperature Range Models A, B, C ......40°C to +85°C Storage Temperature Range ...... 65°C to +150°C Lead Temperature: RU-16 (Vapor Phase, 60 secs) .. +215°C RU-16 (Infrared, 15 secs).......... +220°C
Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
PIN CONFIGURATION
RFBA VREFA IOUTA AGNDA AGNDB IOUTB VREFB RFBB 1 2 3 4 5 6 7 8 16 CLK 15 LDAC 14 MSB 13 VDD 12 DGND 11 CS 10 RS 9 SDI
REV. PrB, 18 FEB '2002
-3-
PRELIMINARY TECHNICAL DATA
AD5545/AD5555
SDI CLK CS L DA C SDO
Figure 1. AD5545 Timing Diagram
A1 A0 D15 D14 D13 D12 D11 D10 D1 D0
INPUT REG LD
tCSS
tDS
tDH
tCH
tCL t PD
tCSH t LDS t LDAC t LDH
SDI CLK CS L DA C
A1 A0 D13 D12 D11 D10 D09 D08
D1 D0
INPUT REG LD
tCSS
tDS
tDH
tCH
tCL t PD
tCSH t LDS t LDAC t LDH
SDO
Figure 2. AD5555 Timing Diagram
Table 1. AD5545 Control-Logic Truth Table
CS
H L L L + H H H H H
CLK LDAC RS
X L + H L X X X X X H H H H H L H + H H H H H H H H H H L L
MSB
X X X X X X X X 0 H
Serial Shift Register Function
No Effect No Effect Shift-Register-Data advanced one bit No Effect No Effect No Effect No Effect No Effect No Effect No Effect
Input Register Function
Latched Latched Latched Latched Selected DAC Updated with current SR contents Latched Latched Latched Latched Data = 0000H Latched Data = 8000H
DAC Register
Latched Latched Latched Latched Latched Transparent Latched Latched Latched Data = 0000H Latched Data = 8000H
Table 2. AD5555 Control-Logic Truth Table
CS
H L L L + H H H H H Notes:
CLK LDAC RS
X L + H L X X X X X H H H H H L H + H H H H H H H H H H L L
MSB
X X X X X X X X 0 H
Serial Shift Register Function
No Effect No Effect Shift-Register-Data advanced one bit No Effect No Effect No Effect No Effect No Effect No Effect No Effect
Input Register Function
Latched Latched Latched Latched Selected DAC Updated with current SR contents Latched Latched Latched Latched Data = 0000H Latched Data = 2000H
DAC Register
Latched Latched Latched Latched Latched Transparent Latched Latched Latched Data = 0000H Latched Data = 2000H
-4-
18 FEB '2002, REV. PrB
PRELIMINARY TECHNICAL DATA
AD5545/AD5555
1. 2. 3. SR = Shift Register + positive logic transition; X Don't Care At power ON both the Input Register and the DAC Register are loaded with all zeros. Table 3. AD5545 Serial Input Register Data Format, Data is loaded in the MSB-First Format. MSB LSB Bit Position B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data Word A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Note: Only the last 18 bits of data clocked into the serial register (Address + Data) are inspected when the CS line's positive edge returns to logic high. At this point an internally generated load strobe transfers the serial register data contents (bits D15-D0) to the decoded DAC-Input-Register address determined by bits A1 and A0. Any extra bits clocked into the AD5545 shift register are ignored, only the last 18 bits clocked in are used. If double buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC Registers. Table 4. AD5555 Serial Input Register Data Format, Data is loaded in the MSB-First Format. MSB LSB Bit Position B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data Word A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Note: Only the last 16 bits of data clocked into the serial register (Address + Data) are inspected when the CS line's positive edge returns to logic high. At this point an internally generated load strobe transfers the serial register data contents (bits D13-D0) to the decoded DAC-Input-Register address determined by bits A1 and A0. Any extra bits clocked into the AD5555 shift register are ignored, only the last 16 bits clocked in are used. If double buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC Registers. Table 5. Address Decode:
A1 0 0 1 1 A0 0 1 0 1 DAC Decoded NONE DAC A DAC B DAC A and B
REV. PrB, 18 FEB '2002
-5-
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