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Part: AD5551
Category:
Data Conversion
-> DAC (Digital to Analog Converters)
-> 10-14 bit
Description: 5V, Serial-Input, Voltage-output 14-Bit DAC
Company: Analog Devices
Datasheet: Download AD5551 datasheet File size : 54 kB
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FEATURES Full 14-Bit Performance 5 V Single Supply Operation Low Power Fast Settling Time Unbuffered Voltage Output Capable of Driving 60 k L oads Directly SPITM/QSPITM/MICROWIRETM-Compatible Interface Standards Power-On Reset Clears DAC Output to 0 V (Unipolar Mode) Schmitt Trigger Inputs for Direct Optocoupler Interface APPLICATIONS Digital Gain and Offset Adjustment Automatic Test Equipment Data Acquisition Systems Industrial Process Control
5 V, Serial-Input Voltage-Output, 14-Bit DACs AD5551/AD5552
FUNCTIONAL BLOCK DIAGRAMS
VDD
AD5551
VREF 14-BIT DAC VOUT
AGND CS DIN SCLK CONTROL LOGIC SERIAL INPUT REGISTER 14-BIT DATA LATCH
DGND
VDD
AD5552
RINV VREFF 14-BIT DAC
RFB RFB INV
VOUT AGNDF
GENERAL DESCRIPTION
VREFS CS LDAC SCLK DIN CONTROL LOGIC SERIAL INPUT REGISTER
The AD5551 and AD5552 are single, 14-bit, serial input, voltage output DACs that operate from a single 5 V ± 10% supply. The AD5551 and AD5552 utilize a versatile 3-wire interface that is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. These DACs provide 14-bit performance without any adjustments. The DAC output is unbuffered, which reduces power consumption and offset errors contributed by an output buffer. With an external op amp the AD5552 can be operated in bipolar mode generating a ± VREF output swing. The AD5552 also includes Kelvin sense connections for the reference and analog ground pins to reduce layout sensitivity. For higher precision applications, please refer to 16-bit DACs AD5541, AD5542, and AD5544. The AD5551 and AD5552 are available in an SO package.
14-BIT DATA LATCH AGNDS
DGND
PRODUCT HIGHLIGHTS
1. Single Supply Operation. The AD5551 and AD5552 are fully specified and guaranteed for a single 5 V ± 10% supply. 2. Low Power Consumption. Typically 1.5 mW with a 5 V supply. 3. 3-Wire Serial Interface. 4. Unbuffered output capable of driving 60 k loads, which reduces power consumption as there is no internal buffer to drive. 5. Power-On Reset Circuitry.
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000
AD5551/AD5552SPECIFICATIONS T = T
Parameter STATIC PERFORMANCE Resolution Relative Accuracy, INL Differential Nonlinearity Gain Error Gain Error Temperature Coefficient Zero Code Error Zero Code Temperature Coefficient AD5552 Bipolar Resistor Matching Bipolar Zero Offset Error Bipolar Zero Temperature Coefficient OUTPUT CHARACTERISTICS Output Voltage Range Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough DAC Output Impedance Power Supply Rejection Ratio DAC REFERENCE INPUT Reference Input Range Reference Input Resistance2 LOGIC INPUTS Input Current VINL, Input Low Voltage VINH, Input High Voltage Input Capacitance3 Hysteresis Voltage3 REFERENCE Reference 3 dB Bandwidth Reference Feedthrough Signal-to-Noise Ratio Reference Input Capacitance POWER REQUIREMENTS V DD IDD Power Dissipation 2.0 9 7.5 0 VR E F 1 25 10 10 6.25 ± 1.0 V DD Min 14 ± 0.15 ± 0.15 1.75 0.3 ± 0.1 0 0.1 ± 0.05 ± 1.0 ± 0.8 0 0.5 Typ Max
(VDD = 5 V 10%, VREF = 2.5 V, AGND = DGND = 0 V. All specifications A MIN to TMAX, unless otherwise noted.)
Unit Bits LSB LSB LSB p p m /° C LSB p p m /° C / % LSB p p m /° C V V µs V/µs nV-s nV-s k LSB V k k µA V V pF V MHz mV p-p dB pF pF All 1s Loaded All 0s Loaded, VREF = 1 V p-p at 100 kHz Code 0000H Code 3FFFH Test Condition
B Grade Guaranteed Monotonic
1.000 ± 0.0015 ± 0.0152 ± 0.25 ± 2.5 ± 0.2 VREF 1 LSB VREF 1 LSB
RFB/RINV, Typically RFB = RINV = 28 k Ratio Error
Unipolar Operation AD5552 Bipolar Operation to 1/2 LSB of FS, CL = 10 pF CL = 10 pF, Measured from 0% to 63% 1 LSB Change Around the Major Carry All 1s Loaded to DAC, VREF = 2.5 V Tolerance Typically 20% VDD ± 10%
Unipolar Operation AD5552, Bipolar Operation
±1 0.8 2.4 10 0.4 1.3 1 92 75 120 4.50 0.3 1.5 5.50 1.1 6.05
V mA mW
NOTES 1 Temperature range is as follows: B Version: 40°C to +85°C. 2 Reference input resistance is code-dependent, minimum at 2555 H. 3 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
2
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AD5551/AD5552 TIMING CHARACTERISTICS1, 2 otherwise noted.)
Parameter fS C L K t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 Limit at TMIN, TMAX All Versions 25 40 20 20 15 15 35 20 15 0 30 30 30
(VDD = 5 V
5%, VREF = 2.5 V, AGND = DGND = 0 V. All specifications TA = TMIN to TMAX, unless
Unit MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min
Description SCLK Cycle Frequency SCLK Cycle Time SCLK High Time SCLK Low Time CS Low to SCLK High Setup CS High to SCLK High Setup SCLK High to CS Low Hold Time SCLK High to CS High Hold Time Data Setup Time Data Hold Time LDAC Pulsewidth CS High to LDAC Low Setup CS High Time Between Active Periods
NOTES 1 Guaranteed by design. Not production tested. 2 Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to 90% of +3 V and timed from a voltage level of +1.6 V). Specifications subject to change without notice.
t1
SCLK
t6 t4
CS
t2
t3 t7
t5
t 12 t8 t9
DB13 DB0
DIN
t 11
LDAC*
*AD5552 ONLY. MAY BE TIED PERMANENTLY LOW IF REQUIRED.
t 10
Figure 1. Timing Diagram
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3
AD5551/AD5552
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +6 V Digital Input Voltage to DGND . . . . . 0.3 V to VDD + 0.3 V VOUT to AGND . . . . . . . . . . . . . . . . . . 0.3 V to VDD + 0.3 V AGND, AGNDF, AGNDS to DGND . . . . . 0.3 V to +0.3 V Input Current to Any Pin Except Supplies . . . . . . . . ± 10 mA Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . 40°C to +85°C Storage Temperature Range . . . . . . . . . . . . 65°C to +150°C Maximum Junction Temperature, (TJ max) . . . . . . . . . 150°C
Package Power Dissipation . . . . . . . . . . . . . (TJ max TA)/JA Thermal Impedance JA SOIC (SO-8) . . . . . . . . . . . . . . . . . . . . . . . . . . 149.5°C/W SOIC (R-14) . . . . . . . . . . . . . . . . . . . . . . . . . . 104.5°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD5551BR AD5552BR
Die Size = 80
INL ± 1 LSB ± 1 LSB
DNL ± 0.8 LSB ± 0.8 LSB
Temperature Range 40°C to +85°C 40°C to +85°C
Package Description 8-Lead Small Outline IC 14-Lead Small Outline IC
Package Option SO-8 R-14
139 = 11,120 sq mil; Number of Transistors = 1230.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5551/AD5552 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
AD5551 PIN FUNCTION DESCRIPTIONS
Mnemonic V OUT AGND V REF CS SCLK DIN DGND V DD
Pin No. 1 2 3 4 5 6 7 8
Description Analog Output Voltage from the DAC. Ground Reference Point for Analog Circuitry. This is the voltage reference input for the DAC. Connect to external reference ranges from 2 V to VDD. This is an active low-logic input signal. The chip select signal is used to frame the serial data input. Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. Serial Data Input. This device accepts 14-bit words. Data is clocked into the input register on the rising edge of SCLK. Digital Ground. Ground reference for digital circuitry. Analog Supply Voltage, 5 V ± 10%.
AD5551 PIN CONFIGURATION SOIC
VOUT 1 AGND 2
8
AD5552 PIN CONFIGURATION SOIC
RFB 1 VOUT 2 AGNDF 3 AGNDS 4
14 VDD 13 INV 12 DGND
VDD DGND
AD5551
7
TOP VIEW VREF 3 (Not to Scale) 6 DIN CS 4
5
SCLK
TOP VIEW 11 LDAC VREFS 5 (Not to Scale) 10 DIN VREFF 6 CS 7
9 8
AD5552
NC SCLK
NC = NO CONNECT
4
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AD5551/AD5552
AD5552 PIN FUNCTION DESCRIPTIONS
Mnemonic RFB V OUT AGNDF AGNDS VREFS V REFF CS SCLK NC DIN LDAC DGND INV VDD
TERMINOLOGY Relative Accuracy
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Description Feedback Resistor. In bipolar mode connect this pin to external op amp output. Analog Output Voltage from the DAC. Ground Reference Point for Analog Circuitry (Force). Ground Reference Point for Analog Circuitry (Sense). This is the voltage reference input (sense) for the DAC. Connect to external reference ranges from 2 V to VDD. This is the voltage reference input (force) for the DAC. Connect to external reference ranges from 2 V to VDD. This is an active low-logic input signal. The chip select signal is used to frame the serial data input. Clock input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. No Connect. Serial Data Input. This device accepts 14-bit words. Data is clocked into the input register on the rising edge of SCLK. LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the input register. Digital Ground. Ground reference for digital circuitry. Connected to the Internal Scaling Resistors of the DAC. Connect INV pin to external op amps inverting input in bipolar mode. Analog Supply Voltage, 5 V ± 10%.
Digital-to-Analog Glitch Impulse
For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL versus code plot can be seen in TPC 1.
Differential Nonlinearity
Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition. A plot of the glitch impulse is shown in TPC 14.
Digital Feedthrough
Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ± 1 LSB maximum ensures monotonicity. TPC 4 illustrates a typical DNL versus code plot.
Gain Error
Gain error is the difference between the actual and ideal analog output range, expressed as a percent of the full-scale range. It is the deviation in slope of the DAC transfer characteristic from ideal.
Gain Error Temperature Coefficient
Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. CS is held high, while the CLK and DIN signals are toggled. It is specified in nV-s and is measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa. A typical plot of digital feedthrough is shown in TPC 13.
Power Supply Rejection Ratio
This is a measure of the change in gain error with changes in temperature. It is expressed in ppm/°C.
Zero Code Error
This specification indicates how the output of the DAC is affected by changes in the power supply voltage. Power-supply rejection ratio is quoted in terms of % change in output per % change in VDD for full-scale output of the DAC. VDD is varied by ± 10%.
Reference Feedthrough
Zero code error is a measure of the output error when zero code is loaded to the DAC register.
Zero Code Temperature Coefficient
This is a measure of the change in zero code error with a change in temperature. It is expressed in mV/°C.
This is a measure of the feedthrough from the VREF input to the DAC output when the DAC is loaded with all 0s. A 100 kHz, 1 V p-p is applied to VREF. Reference feedthrough is expressed in mV p-p.
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