|
|
Part: AD5556CRU
Category:
Description: Current-output Parallel-Input, 14-Bit Digital-to-analog Converter
Company: Analog Devices
Datasheet: Download AD5556CRU datasheet File size : 54 kB
Request For quote: Find where to buy AD5556CRU
Datasheet text preview:
a
Preliminary Technical Data
FEATURES 16-bit Resolution AD5546 14-bit Resolution AD5556 ±1 LSB DNL ±1 or ±2 LSB INL Low Noise 12nV/Hz Low Power, IDD=10µA 0.5µs Settling Time Built-in RFB Facilitates Voltage Conversion Built-in 4-Quadrant Resistors Allow 0 to 10V, 0 to 10V, or +/-10V Outputs 2mA Full Scale Current ± 20%, with VREF=10V Compact TSSOP-28 Packages APPLICATIONS Automatic Test Equipment Instrumentation Digitally Controlled Calibration Digital Waveform Generation
GENERAL DESCRIPTION The AD5546/AD5556 are precision 16/14-bit, low power, currentoutput, parallel input digital-to-analog converters. They are designed to operate from single +5V supply with ±10V multiplying reference for 4-Quadrant outputs. The built-in 4-Quadrant resistors facilitate the resistance matching and temperature tracking that minimize the numbers of components needed for Multi-Quadrant applications. In addition, the feedback resistor (RFB) also simplifies the I-V conversion with an external buffer. The AD5546/AD5556 are packaged in compact TSSOP-28 package and the operating temperature ranges from 40oC to +85oC.
Current-Output Parallel-Input, 16-/14-Bit DAC
AD5546/AD5556
REF ROFS R2 ROFS RFB
FUNCTIONAL DIAGRAMS
R1 R1 VDD RCOM
RFB
AD5546/ AD5556
16/14
DAC
IOUT
WR LDAC DB0-DB15
CRTL LOGIC POR
DAC REGISTER
GND
MSB
RS
Figure 1. 16/14-Bit 4-Quadrant Multiplying DAC with Minimum of External Components
Pr D April 08 `03 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 World Wide Web Site: http://www.analog.com ©Analog Devices, Inc., 2002
Preliminary Technical Data
Range, unless otherwise noted. PARAMETER SYMBOL STATIC PERFORMANCE1 Resolution N Resolution N Relative Accuracy INL Relative Accuracy INL Differential Nonlinearity DNL Output Leakage Current IOUT Output Leakage Current IOUT Full-Scale Gain Error GFSE Full-Scale Tempco2 TCVFS REFERENCE INPUT VREF Range VREF REF Input Resistance REF R1, R2 Resistance R1, R2 Feedback and Offset Resistance RFB, ROFS Input Capacitance2 CREF ANALOG OUTPUT Output Current IOUT Output Capacitance2 COUT LOGIC INPUTS & OUTPUT Logic Input Low Voltage VIL Logic Input High Voltage VIH Input Leakage Current IIL Input Capacitance2 CIL INTERFACE TIMING 2, 3 Data to C Setup Time tDS Data to WR Hold Time tDH WR Pulse Width tWR LDAC Pulse Width tLDAC Reset Pulse Width tRS WR to LDAC Delay Time tLWD SUPPLY CHARACTERISTICS Power Supply Range VDD RANGE Positive Supply Current IDD Power Dissipation PDISS Power Supply Sensitivity PSS NOTES:
1. 2. 3. 4.
AD5546/AD5556
5V±10% AD5546 AD5556 16 14 ±1 ±2 ±1 10 20 ±1/±4 1 -12/+12 5 10 10 5 UNITS Bits Bits LSB max LSB max LSB max nA max nA max
mV typ/max
ELECTRICAL CHARACTERISTICS at VDD = 5V±10%, VSS = 0V, IOUT = Virtual GND, GND=0V, VREF = 10V, TA = Full Operating temperature
CONDITION 1 LSB = VREF/216 = 153µV when VREF = 10V 1 LSB = VREF/214 = 610µV when VREF = 10V Grade: AD5556C Grade: AD5546B Monotonic Data = 0000H, TA = 25°C Data = 0000H, TA = TA MAX Data = FFFFH
ppm/°C typ V min/max k ohm typ4 k ohm typ4 k ohm typ4 pF typ mA typ pF typ V max V min µA max pF max ns min ns min ns min ns min ns min ns min V min/max µA max mW max %/% max
Data = FFFFH Code Dependent
2 200 0.8 2.4 10 10 25 0 25 25 25 0 4.5/5.5 10 0.055 0.006
Logic Inputs = 0V Logic Inputs = 0V VDD = ±5%
All static performance tests (except IOUT) are performed in a closed loop system using an external precision OP177 I-to-V converter amplifier. The AD5546 RFB terminal is tied to the amplifier output. The opamp +IN is grounded and the DAC IOUT is tied to the opamp IN. Typical values represent average readings measured at 25°C These parameters are guaranteed by design and not subject to production testing. All input control signals are specified with tR = tF = 2.5ns (10% to 90% of +3V) and timed from a voltage level of 1.5V. All AC Characteristic tests are performed in a closed loop system using an AD841 I-to-V converter amplifier.
Pr D April 08 `03
-2-
Preliminary Technical Data
ELECTRICAL CHARACTERISTICS at VDD = 5V±10%, IOUT = Virtual GND, GND=0V, VREF = 10V,
TA = Full Operating Temperature Range, unless otherwise noted. PARAMETER AC CHARACTERISTICS4 Output Voltage Settling Time Reference Multiplying BW DAC Glitch Impulse Feed Through Error Digital Feed Through Total Harmonic Distortion Output Spot Noise Voltage NOTES:
1. 2. 3. 4.
AD5546/AD5556
5V±10% 0.5 4 7 -65 7 -85 12 UNITS µs typ MHz typ nV-s typ dB nV-s typ dB typ nV/ rt Hz
SYMBOL tS BW Q VOUT/VREF Q THD eN
CONDITION To ±0.1% of Full Scale, Data = 0000H to FFFFH to 0000H VREF = 5VP-P, Data = FFFFH VREF = 0V, Data 0000H to 8000H to 0000H Data = 0000H, VREF = 100mVrms, same channel WR = 1, LDAC =1, and fCLK = 1MHz VREF = 5VP-P, Data = FFFFH, f=1KHz f = 1kHz, BW = 1Hz
All static performance tests (except IOUT) are performed in a closed loop system using an external precision OP177 I-to-V converter amplifier. The AD5546 RFB terminal is tied to the amplifier output. The opamp +IN is grounded and the DAC IOUT is tied to the opamp IN. Typical values represent average readings measured at 25°C. These parameters are guaranteed by design and not subject to production testing. All input control signals are specified with tR = tF = 2.5ns (10% to 90% of +3V) and timed from a voltage level of 1.5V. All AC Characteristic tests are performed in a closed loop system using an AD841 I-to-V converter amplifier.
Pr D April 08 `03
-3-
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
VDD to GND...... 0.3V, +8V RFB, ROFS, R1, RCOM, and REF to GND .... 18V, 18V Logic Inputs to GND ....... 0.3V, +8V V(IOUT) to GND ...........0.3V, VDD + 0.3V Input Current to Any Pin except Supplies ...... ±50mA Package Power Dissipation........... (TJ MAX TA)/ THETAJA Thermal Resistance THETAJA .... 128°C Maximum Junction Temperature (TJ MAX) ...... 150°C Operating Temperature Range Models B, C ..... 40°C to +85°C Storage Temperature Range ..... 65°C to +150°C Lead Temperature: Vapor Phase, 60 secs ...... +215°C Infrared, 15 secs........ +220°C
Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
AD5546/AD5556
PIN CONFIGURATION
D7 1 D6 2 D5 3 D4 4 D3 5 D2 6 D1 7 D0 8 ROFS RFB R1 RCOM REF IOUT
9 10 11 12 13 14 28 VDD 27 D8 26 D9 25 D10 24 D11 23 D12
AD5546 AD5556
22 D13 21 D14 20 D15 19 GND 18 RS 17 MSB 16 WR 15 LDAC
TSSOP-28
PIN DESCRIPTION
PIN# 1-8 9 10 11 12 13 14 15 16 17 18 19 20-27 28 Name Function D7 to D0 Digital Input Data Bits D7 to D0 ROFS Bipolar Offset Resistor RFB Internal matching Feedback Resistor. Connects to external opamp output for I-V conversion. R1 4-Quandrant Resistor R1. RCOM Reference Input and 4-Quadrant Resistor R2. REF DAC reference input pin. Establishes DAC full-scale voltage. Constant input resistance versus code. IOUT DAC current-output. Connects to inverting terminal of external precision I to V opamp for voltage output. LDAC Digital Input Load DAC Control. WR Write control digital input in active low. Transfers shift-register data to DAC register on rising edge. MSB Power On Reset State. MSB=0 resets at zero-scale, MSB=1 resets at mid-scale. RS Reset. Resets to zero-scale if MSB=0 and resets to mid-scale if MSB=1 GND Analog and Digital Grounds. D15 to D8 Digital Input Data Bits D15 to D8 VDD Positive power supply input. Specified range of operation +5V ±10%.
ORDERING GUIDE
Model
AD5546BRU AD5556CRU
RES (Bit) 16 14
DNL (LSB) ±1 ±1
INL (LSB) ±2 ±1
TEMP
-40 / +85°C -40 / +85°C
Package Description
TSSOP-28 TSSOP-28
Package Option
RU-28 RU-28
The AD5546 contains 1624 transistors. The die size measures 62 mil X 94 mil, 5828 sq mil.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5546/AD5556 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Pr D April 08 `03
-4-
Preliminary Technical Data
tWR
AD5546/AD5556
WR
Data
tDS tDH tLWD
LDAC
tLDAC tRS
RS
Figure 2. AD5546/AD5556 Timing Diagram
Table I. AD5546 Serial Input Register Data Format; Data is loaded in the MSB-First Format. MSB LSB Bit Position B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data Word D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table II. AD5556 Serial Input Register Data Format; Data is loaded in the MSB-First Format. MSB LSB Bit Position B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data Word D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A full 16-bit data word can be loaded into AD5556 serial input register, but only the last 14-bits entered will be transferred to the DAC register when WR returns to logic high. Table III. Control Inputs LDAC RS WR 0 X X 1 0 0 1 1 1 1 0 1 1 1 1 0
Register Operation Reset Output to 0 with MSB=0 and MS with MSB=1 Load Input Register with Data Bits Load DAC Register with the Contents of the Input Register Input and DAC Register are Transparent When LDAC and WR are tied together and programmed as a pulse, the data bits are loaded into the input register on the falling edge of the pulse and then loaded into the DAC Register on the rising edge of the pulse No Register Operation
Pr D April 08 `03
-5-
Others parts begin by ad
AD-1 AD-2 AD-3 AD-4 AD-5 AD-6 AD-7 AD-8 AD-9 AD-10 AD-11 AD-12 AD-13 AD-14 AD-15 AD-16 AD-17 AD-18 AD-19 AD-20 AD-21 AD-22 AD-23 AD-24 AD-25 AD-26 AD-27 AD-28 AD-29 AD-30 AD-31 AD-32 AD-33 AD-34 AD-35 AD-36 AD-37 AD-38 AD-39 AD-40 AD-41 AD-42 AD-43 AD-44 AD-45 AD-46 AD-47 AD-48 AD-49 AD-50 AD-51 AD-52 AD-53 AD-54 AD-55 AD-56 AD-57 AD-58 AD-59 AD-60 AD-61 AD-62 AD-63 AD-64 AD-65 AD-66 AD-67 AD-68 AD-69 AD-70 AD-71 AD-72 AD-73 AD-74 AD-75 AD-76 AD-77 AD-78 AD-79 AD-80 AD-81 AD-82 AD-83 AD-84 AD-85 AD-86 AD-87 AD-88 AD-89 AD-90 AD-91 AD-92 AD-93 AD-94 AD-95 AD-96 AD-97 AD-98 AD-99 AD-100 AD-101 AD-102 AD-103 AD-104 AD-105 AD-106 AD-107
|
|
|