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Part: AD5564
Category:
Description:
Company: Analog Devices
Datasheet: Download AD5564 datasheet File size : 54 kB
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Preliminary Technical Data
FEATURES Infinite Hold Capability with No Droop Single Input, 32/64 channels of Output Input/Output Transfer Function Linearity of ±0.012% max Per-Channel Acquisition time of 16 µs max Input Voltage: 0 to +3V Output Voltage Span: 10.5V e.g. -3V to +7.5V -2.5V to +7V Power-On Reset APPLICATIONS Level Setting Instrumentation Automatic Test Equipment Control Systems Data Acquisition Low Cost I/O
32/64-Channel Infinite Sample-and-Hold AD5532/64
The AD5532/64 combines a 32/64 channel voltage translation function with an infinite output hold capability. An analog input voltage on the common input pin, VI N, is sampled and its digital representation transferred to a chosen DAC register. The output of this DAC is updated to reflect the new contents of the DAC register. Channel selection is accomplished via the parallel address inputs A5-A0 or via the serial input port. The device is operated from +5V, ± 12V to ± 15V supplies and requires a stable +3V reference on REF IN pins as well as an offset voltage on OFFS_IN. The AD5532/64 is available in a 119-lead BGA package.
GENERAL DESCRIPTION
1. No Droop; Infinite Hold Capability 2. Typically ±0.006% transfer function linearity betwen Input and Output. 3. 32/64 14-bit DACs in one package, guaranteed monotonic with 9-bit linearity.
D
FUNCTIONAL BLOCK DIAGRAM
DV C C AV CC REF IN 1 REF IN 2 O FF S _ I N V DD VSS
O
N
A D 5 5 3 2 /6 4
FI
-
EN
3. The AD5532/64 is available in a 119-lead BGA package with a bump pitch of 1.27mm and a body size of 14mm by 22mm.
TI
+ +
A
L
P R O D U C T HIGHLIGHTS
T R AC K B US Y D AC D AC_ GN D AG ND D GN D S E R /P A R I N TE R FA C E CO NT RO L LO G IC ADDRESS INPUT REGISTER WR
C
VIN
ADC
D AC
VO U T 1
V O U T 64
DA C
O FF S _ O U T
Patents Applied For
S CL K
D IN
D O U T SY N C /C S
A5 - A0
CAL
O F FS E T _ S E L
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106,USA Tel: 781/329-4700 World Wide Web: www.analog.com Fax: 781/326-8703
Prelim D3 7/98
AD5532/64-SPECIFICATIONS
Mode 1 - SHA Mode
P a r a m e t e r1 A N A L O G CHANNEL VI N to VOUT Linearity O f f s e t Error Gain Error Channel-to-Channel Matching ANALOG INPUT (VI N) Input Voltage Range Input Current Input Capacitance A N A L O G INPUT (OFFS_IN) Input Current R E F E R E N C E INPUTS Nominal Input Voltage Input Voltage Range Input Current ANALOG OUTPUTS (VOUT 1-64) Output Temp Coeff Output Impedance Output Range Maximum Output Current M a x i m u m Capacitive Load Output Noise S h o r t - C i r c u i t Current Output PSRR DC Crosstalk ANALOG OUTPUT (OFFS_OUT) Output Temp Coeff O u t p u t Impedance Output Range Output Noise Maximum Output Current M a x i m u m Capacitive Load S h o r t - C i r c u i t Current Output PSRR D C Crosstalk D I G I T A L INPUTS Input Current Input Low Voltage Input High Voltage Input Hysteresis (SCLK only) Input Capacitance B Version2 ± 0.012 ± 60 ±3 TBD 0 to +3 100 6.4 50 100 +3.0 +2.85/+3.15 50
VDD = +10.8V to +16.5V, VSS = -10.8V to -16.5V; AVCC = +4.75V to +5.25V; DVCC = +2.7V to +5.25V; AGND = DGND = DAC_GND = 0V; All specifications TMIN to TMAX unless otherwise noted.
Units % max m V max % max % typ V nA max µ A max pF typ nA max V V min/max nA max ppm/°C typ typ V min/max µ A typ n F max µ V rms 1 M H z Bandwidth mA typ dB VDD varied ±5%. dB VSS varied ±5% µ V typ ppm/°C typ k typ V min/max µ V rms µ A typ pF typ mA typ dB typ µ V typ µ A max V max V max V min mV typ p F max Conditions/Comments Typically ±0.006% (after gain and offset adjustment) See Figure 1 (page 8)
Nominal Input Range VI N being acquired on one channel VI N being acquired on all 64 channels simultaneously - Cal Mode
25 750 VSS + 3 /V DD - 3 500 15 250 10 -70 -70 TBD 20 1.0 0 / +REF IN 100 10 100 10 -70 TBD ±10 0.8 0.4 2.0 200 10
1 M H z Bandwidth Source Current S i n k Current AV CC varied ±5%
DVCC = 5V±5% DV CC = 3V±10%
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Prelim D3 7/98
AD5532/64-SPECIFICATIONS
Mode 1 - SHA Mode (cont.)
P a r a m e t e r1 D I G I T A L OUTPUTS (BUSY, D O U T) Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage F l o a t i n g - S t a t e Leakage Current 4 F l o a t i n g - S t a t e Input Capacitance4 P O W E R REQUIREMENTS Power-Supply Voltages VDD VSS AV CC DVCC Power-Supply Currents5 ID D IS S A ICC D I CC P o w e r Dissipation 5 A C CHARACTERISTICS AC Crosstalk Output Settling Time A c q u i s i t i o n Time Slew Rate Digital Feedthrough Digital Crosstalk TRACK MODE Output PSRR Bandwidth B Version2 0.4 4.0 0.4 2.4 TBD TBD
VDD = +10.8V to +16.5V, VSS = -10.8V to -16.5V; AV CC = +4.75V to +5.25V; DVCC = +2.7V to +5.25V; AGND = DGND = DAC_GND = 0V; All specifications TMIN to TMAX unless otherwise noted.
Units V max V min V max V min µA max p F max
Conditions/Comments DVCC DVCC DVCC DVCC = = = = 5V. 5V. 3V. 3V. Sinking TBD mA Sourcing TBD µA Sinking TBD mA Sourcing TBD µA
+10.8/+16.5 -10.8/-16.5 +4.75/+5.25 +2.7/+5.25 22 22 44 <1 880 TBD 1 16 1 TBD TBD TBD TBD TBD
V V V V
min/max min/max min/max min/max
mA typ mA typ mA typ m A max mW typ nV-s typ µs typ µs max V/µs typ nV-s typ nV-s typ dB dB kHz typ
Low Capacitive load Acquire VI N to ± 0.012% accuracy
VD D varied ±5%. VSS varied ±5%
NOTES: 1 See Terminology 2 B Version: Industrial temperature range -40°C. to +85°C. 3 Guaranteed by design and characterisation, not production tested 4 DOUT only 5 Outputs Unloaded. All figures are for the AD5564. The numbers for AD5532 are approx 50% of these. Specifications subject to change without notice
-3-
Prelim D3 7/98
AD5532/64-SPECIFICATIONS
Mode 2 - DAC Mode
P a r a m e t e r1 D C PERFORMANCE Resolution I n t e g r a l Nonlinearity (INL) D i f f e r e n t i a l Nonlinearity (DNL) O f f s e t Error Gain Error Full-Scale Error Offset Error Temp Coeff Gain Error Temp Coeff Channel-to-Channel Matching AC CHARACTERISTICS Output Settling Time OFFS_IN Settling Time Digital-to-Analog Glitch Impulse Digital Crosstalk Analog Crosstalk Total Harmonic Distortion (THD) Output Noise Spectral Density B Version2 14 TBD ±1 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
VDD = +10.8V to +16.5V, VSS = -10.8V to -16.5V; AV CC = +4.75V to +5.25V; DVCC = +2.7V to +5.25V; AGND = DGND = DAC_GND = 0V; All specifications TMIN to TMAX unless otherwise noted.
Units Bits % of FSR typ L S B max m V max % max mV max µV/°C typ µV/°C typ % max µs typ µs typ nV-s typ nV-s typ nV-s typ dB typ nV/(Hz)1/2 typ Conditions/Comments
G u a r a n t e e d Monotonic
NOTES: 1 See Terminology 2 B version: Industrial temperature range -40°C. to +85°C. 3 Guaranteed by design and characterisation, not production tested Specifications subject to change without notice
Timing Characteristics Serial Interface
P a r a m e t e r1 t1 t2 t3 t4 t5 t6 t7 t8 2 t9 2 Limit at TMIN, TMAX (B Version) 25 25 5 TBD 10 5 5 10 20 Units ns ns ns ns ns ns ns ns ns min min min min min min min max max Conditions/Comments SCLK High Pulse Width SCLK Low Pulse Width SYNC Falling Edge to SCLK Falling Edge Setup Time SYNC Low Time DI N Setup Time DI N Hold Time SYNC Falling Edge to SCLK Rising Edge Setup Time SCLK Rising Edge to D OUT Valid SCLK Falling Edge to DOUT High Impedance
NOTES: 1 See Interface Timing Diagrams on following pages 2 These numbers are measured with the load circuit of Figure x
Prelim D3 7/98
AD5532/64 Prelim Technical Information Parallel Interface
P a r a m e t e r1 t1 t2 t3 t4 t5 t6 Limit at TMIN, TMAX (B Version) 0 0 50 50 20 0 Units ns ns ns ns ns ns min min min min min min Conditions/Comments CS to WR Setup Time CS to WR Hold Time CS Pulse Width Low WR Pulse Width Low A5-A0, CAL, OFFS_SEL to WR Setup Time A5-A0, CAL, OFFS_SEL to WR Hold Time
NOTES: 1 S e e Interface Timing Diagrams below
t1 CS t3 t4 WR
t2
Serial Interface Timing Diagrams
C
t1 2
O
N
FI
6 7 9
D
A5 -A 0 , C A L , O FFS _S E L
EN
t5 t6 8 10 L SB
SC LK t3 S YN C
1
3 t2
4
5
t4 D IN MSB
t5
t6
10-Bit Write (SHA Mode and Both Readback Modes)
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5 Prelim D3 7/98
A
L
Parallel Interface Timing Diagram
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