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Part: AD5570
Category:
Description: 12 V/15 V, Serial Input, Voltage Output,16-Bit D/A Converter
Company: Analog Devices
Datasheet: Download AD5570 datasheet File size : 54 kB
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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES Full 16-Bit Performance 1 LSB Max INL and DNL Maximum Output Voltage Range of ±10V Settling Time of 10µs max at 16 bits µ Clear Function to 0 V Asynchronous Update of Outputs (LDAC pin) Power On Reset Serial Data Output for Daisy Chaining Data Readback Facility Temperature Range -40 C to +125 C APPLICATIONS Industrial Automation Automatic Test Equipment Process Control Data Acquisition Systems General Purpose Instrumentation
12 V/15 V, Serial Input Voltage Output, 16 Bit DAC AD5570
F U N C T I O N A L BLOCK DIAGRAM
VSS VDD DGND
AD5570
2*RDAC
POWER ON RESET
REFGND
+
R R R
16 - BIT DAC
+
VOUT AGND AGNDS
REFIN
+
-
R
DAC REGISTER
POWER-DOWN LDAC SHIFT REGISTER CONTROL LOGIC PD
SDIN
SCLK
SYNC
SDO
CLR
G E N E R A L DESCRIPTION
P R O D U C T HIGHLIGHTS
The AD5570 is a single 16-bit serial input, voltage output DAC that operates from supply voltages of ±12 V up to ±15 V. INL and DNL are accurate to 1LSB (max) over the full temperature range of -40°C to +125°C. The AD5570 utilizes a versatile three-wire interface that is c o m p a t i b l e with SPI TM, QSPITM, MICROWIRE TM and DSP interface standards. Data is presented to the part in the format of a sixteen bit serial word. Serial Data is available on the SDO pin for daisy chaining purposes. Data Readback allows the user to read the contents of the DAC register via the SDO pin. During power-up and power-down sequences (when the supply voltages are changing), VOUT is clamped to 0 V via a low impedence path. LDAC may be used to update the output of the DAC. A Power Down (PD) pin allows the DAC to be put into a low power state, and a CLR pin allows the output to be cleared to 0 V. The AD5570 is available in a 16-pin SSOP package.
1 . Buffered Voltage Output up to ±10V. 2 . 1 LSB max INL and DNL 3 . Wide Temperature Range of -40 C to +125 C.
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation.
REV. PrB 10/02
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P O. Box 9106, Norwood, MA 02062-9106, U.S.A. . Te l : 781/329-4700 World Wide Web Site: http://www.analog.com F a x : 781/326-8703 Analog Devices, Inc., 2002
AD5570SPECIFICATIONS1
Parameter ACCURACY Resolution R e l a t i v e Accuracy D i f f e r e n t i a l Nonlinearity Z e r o - S c a l e Error F u l l - S c a l e Error B i p o l a r Zero Error G a i n Temperature Coefficient 2 R E F E R E N C E INPUT R e f e r e n c e Input Range I n p u t Current O / P CHARACTERISTICS Output Voltage Range Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Impulse DAC Output Impedance 2 Digital Feedthrough Power Supply Rejection Ratio L O G I C INPUTS Input Current VINH, Input High Voltage VINL, Input Low Voltage CIN, Input Capacitance2 Hystersis Voltage L O G I C OUTPUTS VOL, Output Low Voltage Floating-State Leakage Current Floating-State O/P Capacitance POWER VDD/VSS REQUIREMENTS ±11.4 ±16.5 5 5 20 1 100 A Grade 16 ±1 ±1 16 16 16 1 3 5 1
PRELIMINARY TECHNICAL DATA
(VDD = +11.4 V to +16.5 V ; VSS = -11.4 V to -16.5 V; VREF = 5V; GND = 0 V; RL = 5 k and CL = 200 pF to GND. All specifications TMIN to TMAX, unless otherwise noted)
Units T e s t Conditions/Comments
LSB LSB LSB LSB LSB ppm ppm
Bits max max G u a r a n t e e d Monotonic Over Temperature max max max FSR/°C typ FSR/°C max
V max µ A max V max V min µs max V/µs typ nV-s typ max nV-s typ dB min µ A max V min V max p F max V typ V max µ A max p F typ V min V max m A max m A max µ A max L S B / V max m W typ ISINK = 1 mA
VDD - 1.4 V VSS + 1.4 V 10 10 12 0.3 5 75 ±1 2.0 0.8 44 0.15 0.4 ±1 3
At 16 bits to 0.5 LSB M e a s u r e d from 10% to 90% 1 LSB Change around the Major Carry
I DD ISS P o w e r - d o w n Current Power Supply Sensitivity 3 Power Dissipation
V OUT Unloaded
V OUT Unloaded
NOTES 1 T e m p e r a t u r e range: 40°C to +125°C. 2 G u a r a n t e e d by design. 3 S e n s i t i v i t y of Gain Error and Bipolar Zero Error to V DD , V SS variations S p e c i f i c a t i o n s subject to change without notice.
2
REV. PrB
PRELIMINARY TECHNICAL DATA AD5570
(VDD = +12 V ±10%, VSS = -12 V ±10% or VDD = +15 V ±10%, VSS =-15 V ±10%; VREF = 5V; GND = 0 V; RL = 5 k and CL = 200 pF to GND. All specifications TMIN to TMAX, unless otherwise noted)
Parameter fMAX t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 11 t 12 t 13 t 14
1 2
STANDALONE TIMING CHARACTERISTICS1,2
Limit at TMIN, TMAX 8 125 50 50 40 30 10 40 40 0 40 0 20 0 40 Units M H z max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min
Description S C L K Frequency SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge M i n SYNC high time SYNC Rising Edge to LDAC Falling Edge L D A C Pulsewidth LDAC Rising Edge to SYNC Falling Edge SCLK Falling Edge to LDAC Rising Edge S C L K Falling Edge to LDAC Falling Edge CLR pulse width
Guaranteed by design and characterization. Not production tested. All input signals are measured with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (V IL +V IH ) / 2 . S p e c i f i c a t i o n s subject to change without notice.
t1 SC LK t2 t8 SYNC t6 t5 SD IN DB1 5 DB0 DB0 t9 LDAC1 t 13 LDAC2 t10 t4 t3 t7
t 11 t12
CLR No t e s 1. A SYN CHRONOUS L DA C UPDA TE MODE 2. SYNC HRONOUS L DA C UPDA T E MODE
t14
Figure 1. Serial Interface Timing Diagram
REV. PrB
3
AD5570
PRELIMINARY TECHNICAL DATA
(VDD = +12 V ±10%, VSS = -12 V ±10% or VDD = +15 V ±10%, VSS =-15 V ±10%; VREF = 5V; GND = 0 V; RL = 5 k and CL = 200 pF to GND. All specifications TMIN to TMAX, unless otherwise noted)
Parameter fMAX t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 11 t 15
1 2
DAISY CHAINING AND READBACK TIMING CHARACTERISTICS1,2,3
Limit at TMIN, TMAX 2 500 200 200 40 30 10 40 40 0 20 0 40 Units M H z max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min Description
S C L K Frequency SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge M i n SYNC high time SYNC Rising Edge to LDAC Falling Edge L D A C Pulsewidth LDAC Rising Edge to SYNC Falling Edge Data delay on SDO
Guaranteed by design and characterization. Not production tested. All input signals are measured with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (V IL +V IH) / 2 . 3 S D O ; R PULLUP = 5k, C L = 15pF. S p e c i f i c a t i o n s subject to change without notice.
t1 SCLK t8 SYNC t10 t9 LDAC2 t5 SDIN DB15 (N) t6 t4 t3 t2 t7 t11
LDAC1
DB0 (N)
DB15 (N+1)
DB0 (N+1) t15
SDO
DB15(N)
DB0(N)
DB15 (N+1)
No t es 1. ASYNCHRONOUS LDAC UPDATE MODE 2. SYNCHRONOUS LDAC UPDATE MODE
Figure 2. Daisy Chaining Timing Diagram
4
REV. PrB
PRELIMINARY TECHNICAL DATA AD5570
t1 SCLK t2 t8 SYNC t6 t5 DIN DB15(N) DB0(N)
DB15 (N+1)
t3 t7
t4
DB0 (N+1)
t10 LDAC t9 t11
SDO
DB15(N)
DB14(N)
DB0(N)
Figure 3. Readback Timing Diagram
A B S O L U T E MAXIMUM RATINGS1
( T A = +25°C unless otherwise noted)
VDD to AGND, DGND .. -0.3 V, +17 V V SS to AGND, DGND.....+0.3 V, -17 V AGND to DGND ...........-0.3 V to VDD to +0.3 V R E F O U T to AGND ..0 V to VDD REFIN to AGND ...........-0.3 V to VDD to +0.3 V D i g i t a l Inputs to DGND........-0.3V to VDD +0.3 V S D O to DGND .. -0.3V to +6.5 V O p e r a t i n g Temperature Range .... 40°C to +125°C S t o r a g e Temperature Range ....... 65°C to +150°C Maximum Junction Temperature, (TJ max) .........+150°C 1 6 - L e a d SSOP Package P o w e r Dissipation ... (TJ max TA)/JA JA Thermal Impedance ....... 139 C / W
L e a d Temperature (Soldering 10s) ..... 3 0 0 ° C I R Reflow, Peak Temperature ....+220 C
NOTES 1 S t r e s s e s above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. E x p o s u r e to absolute maximum rating conditions for extended periods m a y affect device reliability.
O R D E R I N G GUIDE
Model AD5570YRS
Temperature Range -40 °C to +125 °C
Description S h r i n k SO package
Package RS-16
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5570 feature proprietary ESD protection circuitry, permanent damage may o c c u r on devices subjected to high energy electrostatic discharges. Therefore, proper ESDprecautions are recommended to avoid performance degradation or loss of functionality.
REV. PrB
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