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Details, datasheet, quote on part number:AD630JCHIPS
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Datasheet text preview:
a
FEATURES Recovers Signal from +100 dB Noise 2 MHz Channel Bandwidth 45 V/ s Slew Rate 120 dB Crosstalk @ 1 kHz Pin Programmable Closed Loop Gains of 1 and 0.05% Closed Loop Gain Accuracy and Match 100 V Channel Offset Voltage (AD630BD) 350 kHz Full Power Bandwidth Chips Available 2
Balanced Modulator/Demodulator AD630
FUNCTIONAL BLOCK DIAGRAM
CM OFF ADJ
6
CM OFF ADJ
5
DIFF OFF ADJ
4
DIFF OFF ADJ
3
2.5k RINA 1 CHA+ 2 CHA 20 2.5k RINB
7
A MP A
AD630
12
COMP +VS VOUT RB RF RA CHANNEL STATUS B/A
A A MP B
11 13
B V
CHB+ 18 1 CHB 19
10k
1
0k
14 15
8
5k
16 7
PRODUCT DESCRIPTION
COMP SEL B 9 SEL A 10
The AD630 is a high precision balanced modulator which combines a flexible commutating architecture with the accuracy and temperature stability afforded by laser wafer trimmed thin-film resistors. Its signal processing applications include balanced modulation and demodulation, synchronous detection, phase detection, quadrature detection, phase sensitive detection, lock-in amplification and square wave multiplication. A network of on-board applications resistors provides precision closed loop gains of ± 1 and ± 2 with 0.05% accuracy (AD630B). These resistors may also be used to accurately configure multiplexer gains of +1, +2, +3 or +4. Alternatively, external feedback may be employed allowing the designer to implement his own high gain or complex switched feedback topologies. The AD630 may be thought of as a precision op amp with two independent differential input stages and a precision comparator which is used to select the active front end. The rapid response time of this comparator coupled with the high slew rate and fast settling of the linear amplifiers minimize switching distortion. In addition, the AD630 has extremely low crosstalk between channels of 100 dB @ 10 kHz. The AD630 is intended for use in precision signal processing and instrumentation applications requiring wide dynamic range. When used as a synchronous demodulator in a lock-in amplifier configuration, it can recover a small signal from 100 dB of interfering noise (see lock-in amplifier application). Although optimized for operation up to 1 kHz, the circuit is useful at frequencies up to several hundred kilohertz. Other features of the AD630 include pin programmable frequency compensation, optional input bias current compensation resistors, common-mode and differential-offset voltage adjustment, and a channel status output which indicates which of the two differential inputs is active. This device is now available to Standard Military Drawing (DESC) numbers 5962-8980701RA and 5962-89807012A. REV. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
VS
PRODUCT HIGHLIGHTS
1. The configuration of the AD630 makes it ideal for signal processing applications such as: balanced modulation and demodulation, lock-in amplification, phase detection, and square wave multiplication. 2. The application flexibility of the AD630 makes it the best choice for many applications requiring precisely fixed gain, switched gain, multiplexing, integrating-switching functions, and high-speed precision amplification. 3. The 100 dB dynamic range of the AD630 exceeds that of any hybrid or IC balanced modulator/demodulator and is comparable to that of costly signal processing instruments. 4. The op-amp format of the AD630 ensures easy implementation of high gain or complex switched feedback functions. The application resistors facilitate the implementation of most common applications with no additional parts. 5. The AD630 can be used as a two channel multiplexer with gains of +1, +2, +3, or +4. The channel separation of 100 dB @ 10 kHz approaches the limit which is achievable with an empty IC package. 6. The AD630 has pin-strappable frequency compensation (no external capacitor required) for stable operation at unity gain without sacrificing dynamic performance at higher gains. 7. Laser trimming of comparator and amplifying channel offsets eliminates the need for external nulling in most cases.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001
AD630SPECIFICATIONS (@ 25 C and
Model Min GAIN Open Loop Gain ± 1, ± 2 Closed Loop Gain Error Closed Loop Gain Match Closed Loop Gain Drift CHANNEL INPUTS VIN Operational Limit1 Input Offset Voltage Input Offset Voltage TMIN to TMAX Input Bias Current Input Offset Current Channel Separation @ 10 kHz COMPARATOR VIN Operational Limit1 Switching Window Switching Window TMIN to TMAX Input Bias Current Response Time (5 mV to +5 mV Step) Channel Status ISINK @ VOL = VS + 0.4 V2 Pull-Up Voltage DYNAMIC PERFORMANCE Unity Gain Bandwidth Slew Rate3 Settling Time to 0.1% (20 V Step) OPERATING CHARACTERISTICS Common-Mode Rejection Power Supply Rejection Supply Voltage Range Supply Current OUTPUT VOLTAGE, @ RL = 2 k TMIN to TMAX Output Short Circuit Current TEMPERATURE RANGES Rated PerformanceN Package Rated PerformanceD Package 85 90 ±5 90 AD630J/A Typ Max 110 0.1 0.1 2
VS =
Min 100
15 V unless otherwise noted.)
AD630K/B Typ Max 120 0.05 0.05 2 Min 90 AD630S Typ 110 0.1 0.1 2 Max Unit dB % % p p m /° C Volts µV µV nA nA dB Volts mV mV nA ns mA Volts MHz V/µs µs dB dB Volts mA Volts mA °C °C
(VS + 4 V) to (+VS 1 V) 500 800 300 50
(VS + 4 V) to (+VS 1 V) 100 160 300 50
(VS + 4 V) to (+VS 1 V) 500 1000 300 50
100 10 100
100 10 100
100 10 100
(VS + 3 V) to (+VS 1.5 V) ± 1.5 ± 2.0 300
(VS + 3 V) to (+VS 1.5 V) ± 1.5 ± 2.0 300
(VS + 3 V) to (+VS 1.3 V) ± 1.5 ± 2.5 300
100 200 1.6
100 200 1.6
100 200 1.6
(VS + 33 V) 2 45 3 105 110 4 ± 10 25 0 25 70 +85 0 25 ± 16.5 5 90 90 ±5 2 45 3 110 110 4 ± 10 25
(VS + 33 V) 2 45 3 90 90 ±5 110 110 4 ± 10 25 70 +85 N/A 55
(VS + 33 V)
± 16.5 5
± 16.5 5
+125
NOTES 1 If one terminal of each differential channel or comparator input is kept within these limits the other terminal may be taken to the positive supply. 2 ISINK @ VOL = (VS + 1) volt is typically 4 mA. 3 Pin 12 Open. Slew rate with Pins 12 and 13 shorted is typically 35 V/µs. Specifications subject to change without notice.
2
REV. D
AD630
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 600 mW Output Short Circuit to Ground . . . . . . . . . . . . . . . Indefinite Storage Temperature, Ceramic Package . . . 65°C to +150°C Storage Temperature, Plastic Package . . . . . 55°C to +125°C Lead Temperature Range (Soldering, 10 sec) . . . . . . . . 300°C Max Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C
THERMAL CHARACTERISTICS
JC 20-Lead Plastic DIP (N) 20-Lead Ceramic DIP (D) 20-Lead Leadless Chip Carrier (E) 20-Lead SOIC (R-20) 24 °C/W 35 °C/W 35 °C/W 38 °C/W
JA 61 °C/W 120°C/W 120°C/W 75 °C/W
ORDERING GUIDE
Model AD630JN AD630KN AD630AR AD630AR-REEL AD630AD AD630BD AD630SD AD630SD/883B 5962-8980701RA AD630SE/883B 5962-89807012A AD630JCHIPS AD630SCHIPS
Temperature Ranges 0°C to 70°C 0°C to 70°C 25°C to +85°C 25°C to +85°C 25°C to +85°C 25°C to +85°C 55°C to +125°C 55°C to +125°C 55°C to +125°C 55°C to +125°C 55°C to +125°C 0°C to 70°C 55°C to +125°C
Package Description Plastic DIP Plastic DIP SOIC 13" Tape and Reel Side Brazed DIP Side Brazed DIP Side Brazed DIP Side Brazed DIP Side Brazed DIP LCC LCC Chip Chip
Package Option N-20 N-20 R-20 R-20 D-20 D-20 D-20 D-20 D-20 E-20A E-20A
CHIP METALIZATION AND PINOUT
Dimensions shown in inches and (mm). Contact factory for latest dimensions.
PIN CONFIGURATIONS 20-Lead DIP (D-20 and N-20), 20-Lead SOIC (R-20)
RINA 1 CH A+ 2 DIFF OFF ADJ 3 DIFF OFF ADJ 4 CM OFF ADJ 5 20 CH A 19 CH B 18 CH B+ 17 RIN B
AD630
16 RA
TOP VIEW CM OFF ADJ 6 (Not to Scale) 15 RF 14 RB CHANNEL STATUS B/A 7 VS 8 SEL B 9 SEL A 10 13 VOUT 12 COMP 11 +VS
20-Contact LCC (E-20A)
DIFF OFF ADJ CH A+ RIN A CH A CH B
18 CH B+ 17 RIN B 16 RA 15 RF 14 RB 9 10 11 12 13
32
1 20 19
CHIP AVAILABILITY
T h e AD630 is available in laser trimmed, passivated chip form. The figure shows the AD630 metalization pattern, bonding pads and dimensions. AD630 chips are available; consult factory for details.
DIFF OFF ADJ 4 CM OFF ADJ 5 CM OFF ADJ 6 CHANNEL STATUS B/A 7 VS 8
AD630
TOP VIEW (Not to Scale)
SEL B
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD630 features proprietary ESD protection circuitry, permanent damage may occur on devices s u b j e c t e d to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
SEL A +VS
COMP VOUT
WARNING!
ESD SENSITIVE DEVICE
REV. D
3
AD630Typical Performance Characteristics
15
15
18 15 Vi
5k
2 5k
1
O
OUTPUT VOLTAGE
UTPUT VOLTAGE
10 5k k VO 5 2k 100pF
10
OUTPUT VOLTAGE
RL= 2k CL = 100pF
CL = 100pF f = 1kHz
V
V
V
k 10
V 00pF
Vi 5
O
5k 5 Vi
5k
V
O
RL CAP IN
5 f = 1kHz CL = 100pF
100pF
1k
10k
100k
1M
1
10
FREQUENCY Hz
100 1k 10k 100k RESISTIVE LOAD
1M
0
5 10 15 SUPPLY VOLTAGE V
TPC 1. Output Voltage vs. Frequency
TPC 2. Output Voltage vs. Resistive Load
60 UNCOMPENSATED 40
TPC 3. Output Voltage Swing vs. Supply Voltage
120 100
OPEN LOOP GAIN dB
120
COMMON MODE REJECTION dB
0
OPEN LOOP PHASE Degrees
100
UNCOMPENSATED 80
45
V/ s
80
20 0 COMPENSATED 20 40
60 40
DVO
60 COMPENSATED
90
dt
40 20
135
20
0 1
10
100 1k 10k FREQUENCY Hz
100k
60 5 4 3
2 3 2 1 0 1 INPUT VOLTAGE V
4
5
0 10 100 1k 10k 100k FREQUENCY Hz 1M
180 10M
TPC 4. Common-Mode Rejection vs. Frequency
TPC 5.
dVO vs. Input Voltage dt
TPC 6. Gain and Phase vs. Frequency
4
REV. D REV.
AD630
20mV
100 90
10V
10V 20kHz (Vi) 1mV/DIV (B)
100 90
1mV
5s
20mV/DIV (Vo)
20mV/DIV (Vi)
10 0%
10V/DIV (Vo)
10 0%
20mV
TOP TRACE: Vo BOTTOM TRACE: Vi
500ns
10V
TOP TRACE: Vi MIDDLE TRACE: SETTLING ERROR (B) BOTTOM TRACE: Vo
16 5k
15 2 20 19 18 CH B CH A 10k 13 12 VO
i
10k TOP V TRACE 14 10k 15 20 2 CH A 12 H10k P5082-2811 13
1
O
0k
V 10k 14
i
BOTTOM TRACE V (B) MIDDLE TRACE
9 10
TPC 7. Channel-to-Channel Switch-Settling Characteristic
TPC 9. Large Signal Inverting Step Response
50mV
50mV/DIV (Vi) 1mV/DIV (A)
100 90
1mV
10 0%
100mV/DIV (Vo)
100mV
500ns
TOP TRACE: Vi MIDDLE TRACE: SETTLING ERROR (A) BOTTOM TRACE: Vo
10k V
i
1 13 0k
O
14 10k
15 20 2 CH A 12 BOTTOM TRACE V
TOP TRACE
3k 1 0pF
MIDDLE TRACE (A) TEKTRONIX 7A13
10k
TPC 8. Small Signal Noninverting Step Response
REV. D
5
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