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Details, datasheet, quote on part number:AD630SE
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Datasheet text preview:
a
FEATURES Recovers Signal from +100 dB Noise 2 MHz Channel Bandwidth 45 V/ s Slew Rate 120 dB Crosstalk @ 1 kHz Pin Programmable Closed Loop Gains of 1 and 0.05% Closed Loop Gain Accuracy and Match 100 V Channel Offset Voltage (AD630BD) 350 kHz Full Power Bandwidth Chips Available 2
Balanced Modulator/Demodulator AD630
FUNCTIONAL BLOCK DIAGRAM
CM OFF ADJ
6
CM OFF ADJ
5
DIFF OFF ADJ
4
DIFF OFF ADJ
3
2.5k RINA 1 CHA+ 2 CHA 20 2.5k RINB
7
A MP A
AD630
12
COMP +VS VOUT RB RF RA CHANNEL STATUS B/A
A A MP B
11 13
B V
CHB+ 18 1 CHB 19
10k
1
0k
14 15
8
5k
16 7
PRODUCT DESCRIPTION
The AD630 is a high precision balanced modulator which combines a flexible commutating architecture with the accuracy and temperature stability afforded by laser wafer trimmed thin-film resistors. Its signal processing applications include balanced modulation and demodulation, synchronous detection, phase detection, quadrature detection, phase sensitive detection, lock-in amplification and square wave multiplication. A network of on-board applications resistors provides precision closed loop gains of ± 1 and ± 2 with 0.05% accuracy (AD630B). These resistors may also be used to accurately configure multiplexer gains of +1, +2, +3 or +4. Alternatively, external feedback may be employed allowing the designer to implement his own high gain or complex switched feedback topologies. The AD630 may be thought of as a precision op amp with two independent differential input stages and a precision comparator which is used to select the active front end. The rapid response time of this comparator coupled with the high slew rate and fast settling of the linear amplifiers minimize switching distortion. In addition, the AD630 has extremely low crosstalk between channels of 100 dB @ 10 kHz. The AD630 is intended for use in precision signal processing and instrumentation applications requiring wide dynamic range. When used as a synchronous demodulator in a lock-in amplifier configuration, it can recover a small signal from 100 dB of interfering noise (see lock-in amplifier application). Although optimized for operation up to 1 kHz, the circuit is useful at frequencies up to several hundred kilohertz. Other features of the AD630 include pin programmable frequency compensation, optional input bias current compensation resistors, common-mode and differential-offset voltage adjustment, and a channel status output which indicates which of the two differential inputs is active. This device is now available to Standard Military Drawing (DESC) numbers 5962-8980701RA and 5962-89807012A. REV. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
COMP SEL B 9 SEL A 10
VS
PRODUCT HIGHLIGHTS
1. The configuration of the AD630 makes it ideal for signal processing applications such as: balanced modulation and demodulation, lock-in amplification, phase detection, and square wave multiplication. 2. The application flexibility of the AD630 makes it the best choice for many applications requiring precisely fixed gain, switched gain, multiplexing, integrating-switching functions, and high-speed precision amplification. 3. The 100 dB dynamic range of the AD630 exceeds that of any hybrid or IC balanced modulator/demodulator and is comparable to that of costly signal processing instruments. 4. The op-amp format of the AD630 ensures easy implementation of high gain or complex switched feedback functions. The application resistors facilitate the implementation of most common applications with no additional parts. 5. The AD630 can be used as a two channel multiplexer with gains of +1, +2, +3 or +4. The channel separation of 100 dB @ 10 kHz approaches the limit which is achievable with an empty IC package. 6. The AD630 has pin-strappable frequency compensation (no external capacitor required) for stable operation at unity gain without sacrificing dynamic performance at higher gains. 7. Laser trimming of comparator and amplifying channel offsets eliminates the need for external nulling in most cases.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000
AD630SPECIFICATIONS (@ + 25 C and
Model Min GAIN Open Loop Gain ± 1, ± 2 Closed Loop Gain Error Closed Loop Gain Match Closed Loop Gain Drift CHANNEL INPUTS VIN Operational Limit1 Input Offset Voltage Input Offset Voltage TMIN to TMAX Input Bias Current Input Offset Current Channel Separation @ 10 kHz COMPARATOR VIN Operational Limit1 Switching Window Switching Window TMIN to TMAX2 Input Bias Current Response Time (5 mV to +5 mV Step) Channel Status ISINK @ VOL = VS + 0.4 V3 Pull-Up Voltage DYNAMIC PERFORMANCE Unity Gain Bandwidth Slew Rate4 Settling Time to 0.1% (20 V Step) OPERATING CHARACTERISTICS Common-Mode Rejection Power Supply Rejection Supply Voltage Range Supply Current OUTPUT VOLTAGE, @ RL = 2 k TMIN to TMAX2 Output Short Circuit Current TEMPERATURE RANGES Rated PerformanceN Package Rated PerformanceD Package 85 90 5 90 AD630J/A Typ Max 110 0.1 0.1 2
VS =
M in 100
15 V unless otherwise noted)
Min 90 0.05 0.05 2 AD630S Typ 110 0.1 0.1 2 Max Unit dB % % p p m / °C Volts µV µV nA nA dB Volts mV mV nA ns mA Volts MHz V/µs µs dB dB Volts mA Volts mA °C °C
AD630K/B Typ M ax 120
(VS + 4 V) to (+VS 1 V) 500 800 300 50
(VS + 4 V) to (+VS 1 V) 100 160 300 50
(VS + 4 V) to (+VS 1 V) 500 1000 300 50
100 10 100
100 10 100
100 10 100
(VS + 3 V) to (+VS 1.5 V) 1.5 2.0 300
(VS + 3 V) to (+VS 1.5 V) 1.5 2.0 300
(VS + 3 V) to (+VS 1.3 V) 1.5 2.5 300
100 200 1.6
100 200 1.6
100 200 1.6
(VS + 33 V) 2 45 3 105 110 4 10 25 0 25 +70 +85 0 25 ± 16.5 5 90 90 5 2 45 3 110 110 4 10 25
(VS + 33 V) 2 45 3 90 90 5 110 110 4 ± 10 25 +70 +85 N/A 55
(VS + 33 V)
± 16.5 5
± 16.5 5
+125
NOTES 1 If one terminal of each differential channel or comparator input is kept within these limits the other terminal may be taken to the positive supply. 2 These parameters are guaranteed but not tested for J and K grades. For A, B and S grades they are tested. 3 ISINK @ VOL = (VS + 1) volt is typically 4 mA. 4 Pin 12 Open. Slew rate with Pins 12 and 13 shorted is typically 35 V/ µs. Specifications subject to change without notice. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
ABSOLUTE MAXIMUM RATINGS
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 18 V Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 600 mW Output Short Circuit to Ground . . . . . . . . . . . . . . . . Indefinite Storage Temperature, Ceramic Package . . . . 65°C to +150°C Storage Temperature, Plastic Package . . . . . . 55°C to +125°C Lead Temperature Range (Soldering, 10 sec ) . . . . . . . +300°C Max Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C
THERMAL CHARACTERISTICS
Model AD630JN AD630KN AD630AD AD630BD AD630SD AD630SD/883B 5962-8980701RA AD630SE/883B 5962-89807012A AD630JCHIPS AD630SCHIPS
Temperature Ranges 0°C to +70°C 0°C to +70°C 25°C to +85°C 25°C to +85°C 55°C to +125°C 55°C to +125°C 55°C to +125°C 55°C to +125°C 55°C to +125°C 0°C to +70°C 55°C to +125°C
Package Descriptions Plastic DIP Plastic DIP Side Brazed DIP Side Brazed DIP Side Brazed DIP Side Brazed DIP Side Brazed DIP LCC LCC Chip Chip
Package Options N-20 N-20 D-20 D-20 D-20 D-20 D-20 E-20A E-20A
JC 20-Pin Plastic DIP (N) 20-Pin Ceramic DIP (D) 20-Pin Leadless Chip Carrier (E) 24°C/W 35°C/W 35°C/W
JA 6 1° C / W 120°C/W 120°C/W 2
REV. C
AD630
CHIP METALIZATION AND PINOUT
Dimensions shown in inches and (mm). Contact factory for latest dimensions
PIN CONFIGURATIONS 20-Lead DIP (D-20 and N-20)
RINA 1 CH A+ 2 DIFF OFF ADJ 3 DIFF OFF ADJ 4 CM OFF ADJ 5 20 CH A 19 CH B 18 CH B+ 17 RIN B
AD630
16 RA
TOP VIEW CM OFF ADJ 6 (Not to Scale) 15 RF 14 RB CHANNEL STATUS B/A 7 VS 8 SEL B 9 SEL A 10 13 VOUT 12 COMP 11 +VS
20-Contact LCC (E-20A)
DIFF OFF ADJ CH A+ RIN A CH A CH B
18 CH B+ 17 RIN B 16 RA 15 RF 14 RB 9 10 11 12 13 2 5k
32
1 20 19
CHIP AVAILABILITY
DIFF OFF ADJ 4 CM OFF ADJ 5 CM OFF ADJ 6 CHANNEL STATUS B/A 7 VS 8
The AD630 is available in laser trimmed, passivated chip form. The figure shows the AD630 metalization pattern, bonding pads and dimensions. AD630 chips are available; consult factory for details.
AD630
TOP VIEW (Not to Scale)
SEL B
Typical Performance Characteristics
15
15
18 15 Vi
SEL A +VS
COMP VOUT
5k
1
O
OUTPUT VOLTAGE
10 5k k VO 5 2k 100pF
10
OUTPUT VOLTAGE
UTPUT VOLTAGE
RL= 2k CL = 100pF
CL = 100pF f = 1kHz
V
V
V
k 10
V 00pF
Vi 5
O
5k 5 Vi
5k
V
O
RL CAP IN
5 f = 1kHz CL = 100pF
100pF
1k
10k
100k
1M
1
10
FREQUENCY Hz
100 1k 10k 100k RESISTIVE LOAD
1M
0
5 10 15 SUPPLY VOLTAGE V
Figure 1. Output Voltage vs. Frequency
120
COMMON MODE REJECTION dB
Figure 2. Output Voltage vs. Resistive Load
60 UNCOMPENSATED 40
Figure 3. Output Voltage Swing vs. Supply Voltage
120 100
OPEN LOOP GAIN dB
0
OPEN LOOP PHASE Degrees
100
UNCOMPENSATED 80
45
V/ s
80
20 0 COMPENSATED 20 40
60 40
60 COMPENSATED
90
DVO
dt
40 20
135
20
0 1
10
100 1k 10k FREQUENCY Hz
100k
60 5 4 3
0
2 3 2 1 0 1 INPUT VOLTAGE V 4 5
10
100 1k 10k 100k FREQUENCY Hz
1M
180 10M
Figure 4. Common-Mode Rejection vs. Frequency REV. C
Figure 5.
dVO vs. Input Voltage dt 3
Figure 6. Gain and Phase vs. Frequency
AD630 Typical Performance Characteristics
20mV
100 90
50mV
50mV/DIV (Vi) 1mV/DIV (A)
100 90
1mV
10V 20kHz (Vi) 1mV/DIV (B) 10V/DIV (Vo)
100 90
10V
1mV
5s
20mV/DIV (Vo)
20mV/DIV (Vi)
10 0%
10 0%
10 0%
20mV
TOP TRACE: Vo BOTTOM TRACE: Vi
16 5k 15 2 20 19 18 V 10k 14
i
500ns
100mV/DIV (Vo)
100mV
500ns
10V
TOP TRACE: Vi MIDDLE TRACE: SETTLING ERROR (B) BOTTOM TRACE: Vo
10k
i
10k CH A CH B 13 12 VO
V
i
TOP TRACE: Vi MIDDLE TRACE: SETTLING ERROR (A) BOTTOM TRACE: Vo
10k 14 10k 15 20 2 CH A 12 3k 1 0pF 13
1
O
1 13 0k
O
TOP TRACE
0k MIDDLE TRACE (A) TEKTRONIX 7A13
BOTTOM TRACE V
TOP V TRACE
14 10k
15
20 2 CH A 12 H10k BOTTOM TRACE V (B) MIDDLE TRACE
9 10
10k
P5082-2811
Figure 7. Channel-to-Channel SwitchSettling Characteristic
TWO WAYS TO LOOK AT THE AD630
Figure 8. Small Signal Noninverting Step Response
Figure 9. Large Signal Inverting Step Response
The functional block diagram of the AD630 (see page 1) also shows the pin connections of the internal functions. An alternative architectural diagram is shown in Figure 10. In this diagram, the individual A and B channel preamps, the switch, and the integrator output amplifier are combined in a single op amp. This amplifier has two differential input channels, only one of which is active at a time.
VS
15 11 14
16
i
RA 5k
15 2 20 19 A
R
F
10k V 13
O
V
RB 10k 14
18
B
9 10
16
S
2
RA 5k 2.5k A +
RB 10k
Figure 11. AD630 Symmetric Gain (±2)
F
1 20
19 18 17
10k
13
B 2.5k R
12 7
B/A
EL B
9
SEL A 10
8
VS
Figure 10. Architectural Block Diagram
HOW THE AD630 WORKS
When channel B is selected, the resistors RA and RF are connected for inverting feedback as shown in the inverting gain configuration diagram in Figure 12. The amplifier has sufficient loop gain to minimize the loading effect of RB at the virtual ground produced by the feedback connection. When the sign of the comparator input is reversed, input B will be deselected and A will be selected. The new equivalent circuit will be the noninverting gain configuration shown below. In this case RA will appear across the op-amp input terminals, but since the amplifier drives this difference voltage to zero the closed loop gain is unaffected. The two closed loop gain magnitudes will be equal when RF/RA = 1 + RF/RB, which will result from making RA equal to RFRB/ (RF + RB) the parallel equivalent resistance of RF and RB. The 5k and the two 10k resistors on the AD630 chip can be used to make a gain of two as shown here. By paralleling the 10k resistors to make RF equal 5k and omitting RB the circuit can be programmed for a gain of ± 1 (as shown in Figure 18a). These and other configurations using the on chip resistors present the inverting inputs with a 2.5k source impedance. The more complete AD630 diagrams show 2.5k resistors available at the noninverting inputs which can be conveniently used to minimize errors resulting from input bias currents. 4 REV. C
The basic mode of operation of the AD630 may be more easy to recognize as two fixed gain stages which may be inserted into the signal path under the control of a sensitive voltage comparator. When the circuit is switched between inverting and noninverting gain, it provides the basic modulation/demodulation function. The AD630 is unique in that it includes Laser-Wafer-Trimmed thinfilm feedback resistors on the monolithic chip. The configuration shown in Figure 11 yields a gain of ±2 and can be easily changed to ± 1 by shifting RB from its ground connection to the output. The comparator selects one of the two input stages to complete an operational feedback connection around the AD630. The deselected input is off and has negligible effect on the operation.
AD630
F
10k
RA 5k
i
R VO = RF V RA i
faster the output signal will move. This feature helps insure rapid, symmetric settling when switching between inverting and noninverting closed loop configurations. The output section of the AD630 includes a current mirror-load (Q24 and Q25), an integrator-voltage gain stage (Q32), and complementary output buffer (Q44 and Q74). The outputs of both transconductance stages are connected in parallel to the current mirror. Since the deselected input stage produces no output current and presents a high impedance at its outputs, there is no conflict. The current mirror translates the differential output current from the active input transconductance amplifier into single ended form for the output integrator. The complementary output driver then buffers the integrator output produce a low impedance output.
OTHER GAIN CONFIGURATIONS
V
RB 10k
Figure 12. Inverting Gain Configuration
i
RA 5k
R
VO = (1+
RF RB
) Vi
V
R 10k
B
F
10k
Figure 13. Noninverting Gain Configuration
CIRCUIT DESCRIPTION
The simplified schematic of the AD630 is shown in Figure 14. It has been subdivided into three major sections, the comparator, the two input stages and the output integrator. The comparator consists of a front end made up of Q52 and Q53, a flip-flop load formed by Q3 and Q4, and two current steering switching cells Q28, Q29 and Q30, Q31. This structure is designed so that a differential input voltage greater than 1.5 mV in magnitude applied to the comparator inputs will completely select one the switching cells. The sign of this input voltage determine which of the two switching cells is selected.
CH A
20
Many applications require switched gains other than the ± 1 and ± 2 which the self-contained applications resistors provide. The AD630 can be readily programmed with three external resistors over a wide range of positive and negative gain by selecting and RB and RF to give the noninverting gain 1 + RF/RB and subsequent RA to give the desired inverting gain. Note that when the inverting magnitude equals the noninverting magnitude, the value of RA is found to be RB RF/(RB + RF). That is, RA should equal the parallel combination of RB and RF to match positive and negative gain. The feedback synthesis of the AD630 may also include reactive impedance. The gain magnitudes will match at all frequencies if the A impedance is made to equal the parallel combination of the B and F impedances. Essentially the same considerations apply to the AD630 as to conventional op-amp feedback circuits. Virtually any function which can be realized with simple noninverting "L network" feedback can be used with the AD630. A common arrangement is shown in Figure 15. The low frequency gain of this circuit is 10. The response will have a pole (3 dB) at a frequency f 1/(2 100 kC) and a zero (3 dB from the high frequency asymptote) at about 10 times this frequency. The 2k resistor in series with each capacitor mitigates the loading effect on circuitry driving this circuit, eliminates stability problems, and has a minor effect on the pole-zero locations. As a result of the reactive feedback, the high frequency components of the switched input signal will be transmitted at unity gain
C k 102 k 2k 2 100k C V
CH A+
2
CH B+
19
CH B
18
+VS
11
Q33 i55 SEL A
10 9
Q34
Q35
Q36
i73 Q44
Q52
Q53
Q62
Q65
Q67
Q70
13
VO
Q74 C121 Q30 Q31 Q28 Q29 Q24 Q3 Q4 i22 i23 Q25 C122 Q32
12
SEL B
COMP
VS
8 3 4 5 6
DIFF OFF ADJ
DIFF OFF ADJ
CM OFF ADJ
CM OFF ADJ
Vi
Figure 14. AD630 Simplified Schematic
20 19 11.11k 18
A 2
13
O
The collectors of each switching cell connect to an input transconductance stage. The selected cell conveys bias currents i22 and i23 to the input stage it controls, causing it to become active. The deselected cell blocks the bias to its input stage which, as a consequence, remains off. The structure of the transconductance stages is such that they present a high impedance at their input terminals and draw no bias current when deselected. The deselected input does not interfere with the operation of the selected input insuring maximum channel separation. Another feature of the input structure is that it enhances the slew rate of the circuit. The current output of the active stage follows a quasi-hyperbolic-sine relationship to the differential input voltage. This means that the greater the input voltage, the harder this stage will drive the output integrator, and hence, the REV. C 5
B
1
7 9 10 8 VS
Figure 15. AD630 with External Feedback
while the low frequency components will be amplified. This arrangement is useful in demodulators and lock-in amplifiers. It increases the circuit dynamic range when the modulation or interference is substantially larger than the desired signal amplitude. The output signal will contain the desired signal multiplied by the low frequency gain (which may be several hundred for large feedback ratios) with the switching signal and interference superimposed at unity gain.
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