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Part: AD650J
Category:
Analog & Mixed-Signal Processing
-> Power
Description:
Company: Analog Devices
Datasheet: Download AD650J datasheet File size : 445 kB
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a
FEATURES V/F Conversion to 1 MHz Reliable Monolithic Construction Very Low Nonlinearity 0.002% typ at 10 kHz 0.005% typ at 100 kHz 0.07% typ at 1 MHz Input Offset Trimmable to Zero CMOS or TTL Compatible Unipolar, Bipolar, or Differential V/F V/F or F/V Conversion Available in Surface Mount MIL-STD-883 Compliant Versions Available
Voltage-to-Frequency and Frequency-to-Voltage Converter AD650
PIN CONFIGURATION
PRODUCT DESCRIPTION
The AD650 V/F/V (voltage-to-frequency or frequency-to-voltage converter) provides a combination of high frequency operation and low nonlinearity previously unavailable in monolithic form. The inherent monotonicity of the V/F transfer function makes the AD650 useful as a high-resolution analog-to-digital converter. A flexible input configuration allows a wide variety of input voltage and current formats to be used, and an open-collector output with separate digital ground allows simple interfacing to either standard logic families or opto-couplers. The linearity error of the AD650 is typically 20 ppm (0.002% of full scale) and 50 ppm (0.005%) maximum at 10 kHz full scale. This corresponds to approximately 14-bit linearity in an analog-to-digital converter circuit. Higher full-scale frequencies or longer count intervals can be used for higher resolution conversions. The AD650 has a useful dynamic range of six decades allowing extremely high resolution measurements. Even at 1 MHz full scale, linearity is guaranteed less than 1000 ppm (0.1%) on the AD650KN, BD, and SD grades. In addition to analog-to-digital conversion, the AD650 can be used in isolated analog signal transmission applications, phased lockedloop circuits, and precision stepper motor speed controllers. In the F/V mode, the AD650 can be used in precision tachometer and FM demodulator circuits. The input signal range and full-scale output frequency are userprogrammable with two external capacitors and one resistor. Input offset voltage can be trimmed to zero with an external p o t e n t i o m e t e r.
The AD650JN and AD650KN are offered in a plastic 14-lead DIP package. The AD650JP is available in a 20-lead plastic leaded chip carrier (PLCC). Both plastic packaged versions of the AD650 are specified for the commercial (0°C to +70°C) temperature range. For industrial temperature range (25°C to +85°C) applications, the AD650AD and AD650BD are offered in a ceramic package. The AD650SD is specified for the full 55°C to +125°C extended temperature range.
PRODUCT HIGHLIGHTS
1. In addition to very high linearity, the AD650 can operate at full-scale output frequency up to 1 MHz. The combination of these two features makes the AD650 an inexpensive solution for applications requiring high resolution monotonic A/D conversion. 2. The AD650 has a very versatile architecture that can be configured to accommodate bipolar, unipolar, or differential input voltages, or unipolar input currents. 3. TTL or CMOS compatibility is achieved using an open collector frequency output. The pull-up resistor can be connected to voltages up to +30 V, or +15 V or +5 V for conventional CMOS or TTL logic levels. 4. The same components used for V/F conversion can also be used for F/V conversion by adding a simple logic biasing network and reconfiguring the AD650. 5. The AD650 provides separate analog and digital grounds. This feature allows prevention of ground loops in real-world applications. 6. The AD650 is available in versions compliant with MILSTD-883. Refer to the Analog Devices Military Products Databook or current AD650/883B data sheet for detailed specifications.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000
AD650SPECIFICATIONS (@ +25 C, with V =
S
15 V, unless otherwise noted)
Min AD650S Typ Max 1 0.005 0.02 0.05 0.1 Units MHz % % % % % % % of FSR/V
Model DYNAMIC PERFORMANCE Full-Scale Frequency Range Nonlinearity1 fMAX = 10 kHz Nonlinearity1 fMAX = 100 kHz Nonlinearity1 fMAX = 500 kHz Nonlinearity1 fMAX = 1 MHz Full-Scale Calibration Error2, 100 kHz Full-Scale Calibration Error2, 1 MHz vs. Supply3 vs. Temperaturc A, B, and S Grades at 10 kHz at 100 kHz J and K Grades at 10 kHz at 100 kHz BIPOLAR OFFSET CURRENT Activated by 1.24 k Between Pins 4 and 5 DYNAMIC RESPONSE Maximum Settling Time for Full Scale Step Input Overload Recovery Time Step Input ANALOLG INPUT AMPLIFIER (V/F Conversion) Current Input Range (Figure 1) Voltage Input Range (Figure 5) Differential Impedance Common-Mode Impedance Input Bias Current Noninverting Input Inverting Input Input Offset Voltage (Trimmable to Zero) vs. Temperature (TMIN to TMAX) Safe Input Voltage COMPARATOR (F/V Conversion) Logic "0" Level Logic "1" Level Pulse Width Range4 Input Impedance OPEN COLLECTOR OUTPUT (V/F Conversion) Output Voltage in Logic "0" ISINK 8 mA, TMIN to TMAX Output Leakage Current in Logic "1" Voltage Range5 AMPLIFIER OUTPUT (F/V Conversion) Voltage Range (1500 min Load Resistance) Source Current (750 max Load Resistance) Capacitive Load (Without Oscillation) POWER SUPPLY Voltage, Rated Performance Quiescent Current TEMPERATURE RANGE Rated Performance N Package Rated Performance D Package
1 2
AD650J/AD650A Min Typ Max 1 0.005 0.02 0.05
AD650K/AD650B Min Typ Max 1 0.005 0.02 0.05 0.1
0.002 0.005 0.02 0.1 ±5 ± 10 0.015
0.002 0.005 0.02 0.05 ±5 ± 10 0.015
0.002 0.005 0.02 0.05 ±5 ± 10 0.015
+0.015
+0.015
+0.015
± 75 ± 150 ± 75 ± 150 0.45 0.5 0.55 0.45 ± 75 ± 150 0.5
± 75 ± 150
± 75 ± 150
p p m / °C p p m / °C p p m / °C p p m / °C
0.55
0.45
0.5
0.55
mA
1 Pulse of New Frequency Plus 1 µs 1 Pulse of New Frequency Plus 1 µs 0 10 2 M 10 pF 1000 M 10 pF 40 ±8 100 20 4 +0.6 0
1 Pulse of New Frequency Plus 1 µs 1 Pulse of New Frequency Plus 1 µs 0 10 2 M 10 pF 1000 M 10 pF 40 ±8 100 20 4 ± 30 +0.6 0
1 Pulse of New Frequency Plus 1 µs 1 Pulse of New Frequency Plus 1 µs 0 10 2 M 10 pF 1000 M 10 pF 40 ±8 100 20 4 ± 30 nA nA mV µ V/°C C +0.6 0 mA V
± 30 ± VS VS 0 0.1 250
± VS 1 VS +VS 0 (0.3 × tOS) 0.1 250
± VS
1 VS +VS 0 (0.3 × tOS) 0.1 250
+1 V +VS V (0.3 × tOS) µs k
0 0 10
0.4 100 +36 +10 100
0 0 10
0.4 100 +36 +10 100
0 0 10
0.4 100 +36 +10 100
V nA V V mA pF V mA °C °C
±9 8 0 25
18
±9 8 0 25
18
±9 8
18
+70 +85
+70 +85
55
+125
NOTES Nonlinearity is defined as deviation from a straight line from zero to full scale, expressed as a fraction of full scale. Full-scale calibration error adjustable to zero. 3 Measured at full-scale output frequency of 100 kHz. 4 Refer to F/V conversion section of the text. 5 Referred to digital ground. Specifications subject to change without notice. Specifications shown in boldface are tested on all production units at final electrical test. Results from those test are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
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AD650
ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Total Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V Storage Temperature . . . . . . . . . . . . . . . . . . . 55°C to +150°C Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 10 V Maximum Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS Open Collector Output Voltage Above Digital GND . . . . . 36 V Open Collector Output Current . . . . . . . . . . . . . . . . . . 50 mA Amplifier Short Circuit to Ground . . . . . . . . . . . . . . Indefinite Comparator Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . ± VS
D-14 V OUT +IN IN BIPOLAR OFFSET CURRENT V S ONE SHOT CAPACITOR NC F OUTPUT COMPARATOR INPUT DIGITAL GND ANALOG GND +V S OFFSET NULL OFFSET NULL
N-14 V OUT +IN IN BIPOLAR OFFSET CURRENT V S ONE SHOT CAPACITOR NC F OUTPUT COMPARATOR INPUT DIGITAL GND ANALOG GND +V S OFFSET NULL OFFSET NULL
P-20A NC VO U T +IN IN NC BIPOLAR OFFSET CURRENT NC VS ONE SHOT CAPACITOR NC NC FOUTPUT COMPARATOR INPUT DIGITAL GND NC ANALOG GND NC + VS OFFSET NULL OFFSET NULL
ORDERING GUIDE
Model AD650JN AD650KN AD650JP AD650AD AD650BD AD650SD
Gain Tempco ppm/ C 100 kHz 150 typ 150 typ 150 typ 150 max 150 max 150 max
1 MHz Linearity 0.1% typ 0.1% max 0.1% typ 0.1% typ 0.1% max 0.1% max
Specified Temperature Range C 0 to +70 0 to +70 0 to +70 25 to +85 25 to +85 55 to +125
Package Description Plastic DIP Plastic DIP Plastic Leaded Chip Carrier (PLCC) Ceramic DIP Ceramic DIP Ceramic DIP
Package Option N-14 N-14 P-20A D-14 D-14 D-14
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3
AD650
CIRCUIT OPERATION
UNIPOLAR CONFIGURATION
The AD650 is a charge balance voltage-to-frequency converter. In the connection diagram shown in Figure 1, or the block diagram of Figure 2a, the input signal is converted into an equivalent current by the input resistance RIN. This current is exactly balanced by an internal feedback current delivered in short, timed bursts from the switched 1 mA internal current source. These bursts of current may be thought of as precisely defined packets of charge. The required number of charge packets, each producing one pulse of the output transistor, depends upon the amplitude of the input signal. Since the number of charge packets delivered per unit time is dependent on the input signal amplitude, a linear voltage-to-frequency transformation will be accomplished. The frequency output is furnished via an open collector transistor. A more rigorous analysis demonstrates how the charge balance voltage-to-frequency conversion takes place. A block diagram of the device arranged as a V-to-F converter is shown in Figure 2a. The unit is comprised of an input integrator, a current source and steering switch, a comparator and a one-shot. When the output of the one-shot is low, the current steering switch S1 diverts all the current to the output of the op amp; this is called the Integration Period. When the one-shot has been triggered and its output is high, the switch S1 diverts all the current to the summing junction of the op amp; this is called the Reset Period. The two different states are shown in Figure 2 along with the various branch currents. It should be noted that the output current from the op amp is the same for either state, thus minimizing transients.
Figure 2b. Reset Mode
Figure 2c. Integrate Mode
Figure 2d. Voltage Across CINT
The positive input voltage develops a current (IIN = VIN/RIN) which charges the integrator capacitor CINT. As charge builds up on CINT, the output voltage of the integrator ramps downward towards ground. When the integrator output voltage (Pin 1) crosses the comparator threshold (0.6 volt) the comparator triggers the one shot, whose time period, tOS is determined by the one shot capacitor COS. Specifically, the one shot time period is:
tOS = COS × 6. 8 × 103 sec /F + 3. 0 × 107 sec
(1)
The Reset Period is initiated as soon as the integrator output voltage crosses the comparator threshold, and the integrator ramps upward by an amount: V = tOS · dV tOS = (1 mA I N ) dt CINT (2)
After the Reset Period has ended, the device starts another Integration Period, as shown in Figure 2, and starts ramping downward again. The amount of time required to reach the comparator threshold is given as:
Figure 1. Connection Diagram for V/F Conversion, Positive Input Voltage
t /C (1 mA IIN ) 1 mA TI = V = OS INT = tOS 1 dV IIN IN /CINT dt
(3)
The output frequency is now given as:
f OUT = IIN V IN /RIN 1 = = 0.15 F · Hz tOS + T I tOS × 1 mA A COS + 4. 4 × 1011F
(4)
Note that CINT, the integration capacitor has no effect on the transfer relation, but merely determines the amplitude of the sawtooth signal out of the integrator.
One Shot Timing
Figure 2a. Block Diagram
A key part of the preceding analysis is the one shot time period that was given in equation (1). This time period can be broken down into approximately 300 ns of propagation delay, and a second time segment dependent linearly on timing capacitor COS. When the one shot is triggered, a voltage switch that holds Pin 6 4 REV. C
AD650
at analog ground is opened allowing that voltage to change. An internal 0.5 mA current source connected to Pin 6 then draws its current out of COS, causing the voltage at Pin 6 to decrease linearly. At approximately 3.4 V, the one shot resets itself, thereby ending the timed period and starting the V/F conversion cycle over again. The total one shot time period can be written mathematically as:
tOS = V COS + TGATE IDISCHARGE
DELAY
(5)
substituting actual values quoted above,
tOS = 3. 4 V × COS + 300 × 109 sec 0. 5 × 103 A
(6)
Figure 3a. Full-Scale Frequency vs. COS
This simplifies into the timed period equation given above.
COMPONENT SELECTION
Only four component values must be selected by the user. These are input resistance RIN, timing capacitor COS, logic resistor R2, and integration capacitor CINT. The first two determine the input voltage and full-scale frequency, while the last two are determined by other circuit considerations. Of the four components to be selected, R2 is the easiest to define. As a pull-up resistor, it should be chosen to limit the current through the output transistor to 8 mA if a TTL maximum VOL of 0.4 V is desired. For example, if a 5 V logic supply is used, R2 should be no smaller than 5 V/8 mA or 625 . A larger value can be used if desired. RIN and COS are the only two parameters available to set the full- scale frequency to accommodate the given signal range. The "swing" variable that is affected by the choice of RIN and COS is nonlinearity. The selection guide of Figure 3 shows this quite graphically. In general, larger values of COS and lower full-scale input currents (higher values of RIN) provide better linearity. In Figure 3, the implications of four different choices of RIN are shown. Although the selection guide is set up for a unipolar configuration with a zero to 10 V input signal range, the results can be extended to other configurations and input signal ranges. For a full scale frequency of 100 kHz (corresponding to 10 V input), you can see that among the available choices, RIN = 20 k and COS = 620 pF gives the lowest nonlinearity, 0.0038%. Also, if you wish to use the highest frequency that will give the 20 ppm minimum nonlinearity, it is approximately 33 kHz (40.2 k and 1000 pF). For input signal spans other than 10 V, the input resistance must be scaled proportionately. For example, if 100 k is called out for a 0 V10 V span, 10k would be used with a 0 V1 V span, or 200 k with a ± 10 V bipolar connection. The last component to be selected is the integration capacitor CINT. In almost all cases, the best value for CINT can be calculated using the equation:
4 CINT = 10 F / sec (1000 pF min imum) f MAX
Figure 3b. Typical Nonlinearity vs. COS
can be rejected. If the output frequency is measured by counting pulses during a constant gate period, the integration provides infinite normal-mode rejection for frequencies corresponding to the gate period and its harmonics. However, if the integrator stage becomes saturated by an excessively large noise pulse, the continuous integration of the signal will be interrupted, allowing the noise to appear at the output. If the approximate amount of noise that will appear on CINT is known (VNOISE), the value of CINT can be checked using the following inequality:
CINT >
tOS × 1 × 10 3 A +V S 3V V NOISE
(8)
(7)
When the proper value for CINT is used, the charge balance architecture of the AD650 provides continuous integration of the input signal, hence large amounts of noise and interference
For example, consider an application calling for a maximum frequency of 75 kHz, a 0 volt1 volt signal range, and supply voltages of only ± 9 volts. The component selection guide of Figure 3 is used to select 2.0 k for RIN and 1000 pF for COS. This results in a one shot time period of approximately 7 µs. Substituting 75 kHz into equation 7 yields a value of 1300 pF for CINT. When the input signal is near zero, 1 mA flows through the integration capacitor to the switched current sink during the reset phase, causing the voltage across CINT to increase by approximately 5.5 volts. Since the integrator output stage requires approximately 3 volts head room for proper operation, only 0.5 volt margin remains for integrating extraneous noise on the signal line. A negative noise pulse at this time might saturate the integrator, causing an error in signal integration. Increasing CINT to 1500 pF or 2000 pF will provide much more noise margin, thereby eliminating this potential trouble spot. 5
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