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Part: AD652
Category:
Analog & Mixed-Signal Processing
-> Voltage to Frequency/Frequency to Voltage
Description: Monolithic Synchronous Voltage-to-frequency Converter
Company: Analog Devices
Datasheet: Download AD652 datasheet File size : 445 kB
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a
FEATURES Full-Scale Frequency (Up to 2 MHz) Set by External System Clock Extremely Low Linearity Error (0.005% max at 1 MHz FS, 0.02% max at 2 MHz FS) No Critical External Components Required Accurate 5 V Reference Voltage Low Drift (25 ppm/ C max) Dual or Single Supply Operation Voltage or Current Input MIL-STD-883 Compliant Versions Available
Monolithic Synchronous Voltage-to-Frequency Converter AD652
FUNCTIONAL BLOCK DIAGRAM
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD652 Synchronous Voltage-to-Frequency Converter (SVFC) is a powerful building block for precision analog-todigital conversion, offering typical nonlinearity of 0.002% (0.005% maximum) at a 100 kHz output frequency. The inherent monotonicity of the transfer function and wide range of clock frequencies allows the conversion time and resolution to be optimized for specific applications. The AD652 uses a variation of the popular charge-balancing technique to perform the conversion function. The AD652 uses an external clock to define the full-scale output frequency, rather than relying on the stability of an external capacitor. The result is a more stable, more linear transfer function, with significant application benefits in both single- and multichannel systems. Gain drift is minimized using a precision low drift reference and low TC on-chip thin-film scaling resistors. Furthermore, the initial gain error is reduced to less than 0.5% by the use of laser-wafer-trimming. The analog and digital sections of the AD652 have been designed to allow operation from a single-ended power source, simplifying its use with isolated power supplies. The AD652 is available in five performance grades. The 20-pin PLCC packaged JP and KP grades are specified for operation over the 0°C to +70°C commercial temperature range. The 16pin cerdip-packaged AQ and BQ grades are specified for operation over the 40°C to +85°C industrial temperature range, and the AD652SQ is available for operation over the full 55°C to +125°C extended temperature range.
1. The use of an external clock to set the full-scale frequency allows the AD652 to achieve linearity and stability far superior to other monolithic VFCs. By using the same clock to drive the AD652 and (through a suitable divider) also set the counting period, conversion accuracy is maintained independent of variations in clock frequency. 2. The AD652 Synchronous VFC requires only a single external component (a noncritical integrator capacitor) for operation. 3. The AD652 includes a buffered, accurate 5 V reference which is available to the user. 4. The clock input of the AD652 is TTL and CMOS compatible and can also be driven by sources referred to the negative power supply. The flexible open-collector output stage provides sufficient current sinking capability for TTL and CMOS logic, as well as for optical couplers and pulse transformers. A capacitor-programmable one-shot is provided for selection of optimum output pulse width for power reduction. 5. The AD652 can also be configured for use as a synchronous F/V converter for isolated analog signal transmission. 6. The AD652 is available in versions compliant with MILSTD-883. Refer to the Analog Devices Military Products Databook or current AD652/883B data sheet for detailed specifications.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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AD652SPECIFICATIONS (typical @ T = + 25 C, V =
A S
15 V, unless otherwise noted)
Min AD652KP/BQ Typ Max Units
Parameter VOLTAGE-TO-FREQUENCY MODE Gain Error fCLOCK = 200 kHz fCLOCK = 1 MHz fCLOCK = 4 MHz Gain Temperature Coefficient fCLOCK = 200 kHz fCLOCK = 1 MHz fCLOCK = 4 MHz Power Supply Rejection Ratio Linearity Error fCLOCK = 200 kHz fCLOCK = 1 MHz fCLOCK = 2 MHz fCLOCK = 4 MHz Offset (Transfer Function, RTI) Offset Temperature Coefficient Response Time FREQUENCY-TO-VOLTAGE MODE Gain Error fIN = 100 kHz FS Linearity Error fIN = 100 kHz FS INPUT RESISTORS Cerdip (Figure 1a)(0 to +10 V FS Range) PLCC (Figure lb) Pin 8 to Pin 7 Pin 7 to Pin 5 (0 V to +5 V FS Range) Pin 8 to Pin 5 (0 V to +10 V FS Range) Pin 9 to Pin 5 (0 V to +8 V FS Range) Pin 10 to Pin 5 (Auxiliary Input) Temperature Coefficient (All) INTEGRATOR OP AMP Input Bias Current Inverting Input (Pin 5) Noninverting Input (Pin 6) Input Offset Current Input Offset Current Drift Input Offset Voltage Input Offset Voltage Drift Open Loop Gain Common-Mode Input Range CMRR Bandwidth Output Voltage Range (Referred to Pin 6, R1 > = 5k) COMPARATOR Input Bias Current Common-Mode Voltage CLOCK INPUT Maximum Frequency Threshold Voltage (Referred to Pin 12) TMIN to TMAX Input Current (VS
Min
AD625JP/AQ/SQ Typ Max
± 0.5 ± 0.5 ± 0.5 ± 25 ± 25 ± 10 ± 25 0.001
±1 1 1.5 ± 50 50 50 75 0.01
± 0.25 ± 0.25 ± 0.25 ± 15 ± 15 ± 10 ± 15 0.001
± 0.5 0.5 0.75 ± 25 25 30 50 0.01
% % % ppm/ °C ppm/ °C p p m / ° C1 ppm/ °C %/V % % % % mV µV/°C
± 0.002 ± 0.02 ± 0.002 ± 0.005 ± 0.002 0.02 ± 0.002 0.005 ± 0.01 ± 0.02 ± 0.002 ± 0.005 ± 0.02 0.05 ± 0.01 0.02 ±1 3 ±1 2 ± 10 50 ± 10 25 One Period of New Output Frequency Plus One Clock Period.
± 0.5 ± 0.002 19.8 9.9 9.9 19.8 15.8 19.8 20 10 10 20 16 20 ± 50
±1 ± 0.02 20.2 10.1 10.1 20.2 16.2 20.2 100 19.8 9.9 9.9 19.8 15.8 19.8
± 0.25 ± 0.002 20 10 10 20 16 20 ± 50
± 0.5 ± 0.01 20.2 10.1 10.1 20.2 16.2 20.2 100
% % k k k k k k ppm/ °C
±5 20 20 1 ±1 ± 10 86 VS + 5 80 14 1
20 50 70 3 3 ± 25 +V S 5 VS + 5 80 14 1
±5 20 20 1 ±1 ± 10 86
95 (+VS 4)
95
nA nA nA nA/ °C mV µV/°C dB + VS 5 V dB MHz (+VS 4) V
20 50 70 2 2 ± 15
0.5 VS + 4 4 0.8 5 VS 5 1.2
5 + VS 4
0.5 VS + 4 4 5 1.2
5 + VS 4
µA V MHz V V µA V µs REV. A
2.0 20 +V S 2 2
0.8 5 VS
2.0 20 + VS 2
AD652
Parameter OUTPUT STAGE VOL (IOUT = 10 mA) IOL VOL<0.8 V VOL<0.4 V, TMINTMAX IOH (Off Leakage) Delay Time, Positive Clock Edge to Output Pulse Fall Time (Load = 500 pF and ISINK = 5 mA) Output Capacitance OUTPUT ONE-SHOT Pulse Width COS = 300 pF COS = 1000 pF REFERENCE OUTPUT Voltage Drift Output Current Source TMIN to TMAX Sink Power Supply Rejection (Supply Range = ±12.5 V to ± 17.5 V) Output Impedance (Sourcing Current) POWER SUPPLY Rated Voltage Operating Range Dual Supplies Single Supply (VS = 0) Quiescent Current Digital Common Analog Common TEMPERATURE RANGE Specified Performance JP, KP Grade AQ, BQ Grade SQ Grade Min AD625JP/AQ/SQ Typ Max 0.4 15 8 10 250 Min AD652KP/BQ Typ Max 0.4 15 8 10 250 100 5 Units V mA mA µA ns ns pF
150
0.01 200 100 5
150
0.01 200
1 4 4.950
1.5 5 5.0
2 6 5.050 100
1 4 4.975
1.5 5 5.0
2 6 5.025 50
µs µs V ppm/ °C mA µA
10 100
500 0.015 2
10 100
500 0.015 2
0.3 ± 15 ±6 +12 VS VS ± 15 ± 11
0.3 +15
%/V V
± 18 +36 15 +V S 4 +V S
±6 +12 VS VS
± 15 ± 11
± 18 +36 15 + VS 4 + VS
V V mA V V
0 40 55
+70 +85 +125
0 40
+70 +85
°C °C °C
NOTES 1 Referred to internal VREF. In PLCC package, tested on 10 V input range only. Specifications in boldface are 100% tested at final test and are used to measure outgoing quality levels. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
DEFINITIONS OF SPECIFICATIONS
Total Supply Voltage +VS to VS . . . . . . . . . . . . . . . . . . 36 V Maximum Input Voltage (Figure 6) . . . . . . . . . . . . . . . . . 36 V Maximum Output Current (Open Collector Output) . . 50 mA Amplifier Short Circuit to Ground . . . . . . . . . . . . . . Indefinite Storage Temperature Range: Cerdip . . . . . . 65°C to +150°C Storage Temperature Range: PLCC . . . . . . 65°C to +150°C
GAIN ERROR--The gain of a voltage-to-frequency converter is that scale factor setting that provides the nominal conversion relationship, e.g., 1 MHz full scale. The "gain error" is the difference in slope between the actual and ideal transfer functions for the V-F converter. LINEARITY ERROR--The "linearity error" of a V-F is the deviation of the actual transfer function from a straight line passing through the endpoints of the transfer function. GAIN TEMPERATURE COEFFICIENT--The gain temperature coefficient is the rate of change in full-scale frequency as a function of the temperature from +25°C to TMIN or TMAX.
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3
AD652
ORDERING GUIDE
Gain Drift ppm/°C 1 MHz 100 kHz Linearity % 50 max 25 max 50 max 25 max 50 max 0.02 max 0.005 max 0.02 max 0.005 max 0.02 max Specified Temperature Package Range °C Options2 0 to +70 0 to +70 40 to +85 40 to +85 55 to +125 PLCC (P-20A) PLCC (P-20A) Cerdip (Q-16) Cerdip (Q-16) Cerdip (Q-16)
Part Numberl AD652JP AD652KP AD652AQ AD652BQ AD652SQ
NOTES 1 For details on grade and package offerings screened in accordance with MIL-STD883, refer to the Analog Devices Military Products Databook or current AD652/ 883 data sheet. 2 P = Plastic Leaded Chip Carrier; Q = Cerdip; E = Leadless Ceramic Chip Carrier.
Figure 1a. Cerdip Pin Configuration
PIN CONFIGURATIONS
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 "Q" CERDIP + VS TRIM TRIM OP AMP OUT OP AMP "--" OP AMP "+" 10 VOLT INPUT V S C OS CLOCK INPUT FREQ OUT DIGITAL GND ANALOG GND COMP "--" COMP "+" COMP REF "P" PLCC NC + VS NC OP AMP OUT OP AMP "--" OP AMP "+" 5 VOLT INPUT 10 VOLT INPUT 8 VOLT INPUT OPTIONAL 10 V INPUT V S COS CLOCK INPUT FREQ OUT DIGITAL GROUND ANALOG GND COMP "--" COMP "+" NC COMP REF
The pinouts of the AD652 SVFC are shown in Figure 1. A block diagram of the device configured as a SVFC, along with various system waveforms, is shown in Figure 2.
THEORY OF OPERATION
A synchronous VFC is similar to other voltage-to-frequency converters in that an integrator is used to perform a chargebalance of the input signal with an internal reference current. However, rather than using a one-shot as the primary timing element which requires a high quality and low drift capacitor, a synchronous voltage-to-frequency converter (SVFC) uses an external clock; this allows the designer to determine the system stability and drift based upon the external clock selected. A crystal oscillator may also be used if desired. The SVFC architecture provides other system advantages besides low drift. If the output frequency is measured by counting pulses gated to a signal which is derived from the clock, the clock stability is unimportant and the device simply performs as a voltage controlled frequency divider, producing a high resolution A/D. If a large number of inputs must be monitored simultaneously in a system, the controlled timing relationship between the frequency output pulses and the user supplied clock greatly simplifies this signal acquisition. Also, if the clock signal is provided by a VFC, then the output frequency of the SVFC will be proportional to the product of the two input voltages. Hence, multiplication and A-to-D conversion on two signals are performed simultaneously.
Figure 1b. PLCC Pin Configuration
Figure 2 shows the typical up-and-down ramp integrator output of a charge-balance VFC. After the integrator output has crossed the comparator threshold and the output of the AND gate has gone high, nothing happens until a negative edge of the clock comes along to transfer the information to the output of the D-FLOP. At this point, the clock level is low, so the latch does not change state. When the clock returns high, the latch output goes high and drives the switch to reset the integrator. At the same time the latch drives the AND gate to a low output state. On the very next negative edge of the clock the low output state of the AND gate is transferred to the output of the D-FLOP and then when the clock returns high, the latch output goes low and drives the switch back into the Integrate Mode. At the same time the latch drives the AND gate to a mode where it will truthfully relay the information presented to it by the comparator. Since the reset pulses applied to the integrator are exactly one clock period long, the only place where drift can occur is in a variation of the symmetry of the switching speed with temperature. Since each reset pulse is identical to every other, the AD652 SVFC produces a very linear voltage to frequency transfer rela4 REV. A
AD652
tion. Also, since all of the reset pulses are gated by the clock, there are no problems with dielectric absorption causing the duration of a reset pulse to be influenced by the length of time since the last reset. cessive cycle, until finally, a whole cycle is lost. When the cycle is lost, the Integrate Phase lasts for two periods of the clock instead of the usual three periods. Thus, among a long string of divide-by-fours an occasional divide-by-three occurs; the average of the output frequency is very close to one quarter of the clock, but the instantaneous frequency can be very different. Because of this, it is very difficult to observe the waveform on an oscilloscope. During all of this time, the signal at the output of the integrator is a sawtooth wave with an envelope which is also a sawtooth. This is shown in Figure 4.
Figure 4. Integrator Output for IIN Slightly Greater than 250 µA
Figure 2. AD652 Block Diagram and System Waveforms
Referring to Figure 2, it can be seen that the period between output pulses is constrained to be an exact multiple of the clock period. Consider an input current of exactly one quarter of the value of the reference current. In order to achieve a charge balance, the output frequency will equal the clock frequency divided by four; one clock period for reset and three clock periods of integrate. This is shown in Figure 3. If the input current is increased by a very small amount, the output frequency should also increase by a very small amount. Initially, however, no out
Another way to view this is that the output is a frequency of approximately one quarter of the clock that has been phase modulated. A constant frequency can be thought of as accumulating phase linearly with time at a rate equal to 2 f radians per second. Hence, the average output frequency which is slightly in excess of a quarter of the clock will require phase accumulation at a certain rate. However, since the SVFC is running at exactly one quarter of the clock, it will not accumulate enough phase (see Figure 5). When the difference between the required phase (average frequency) and the actual phase equals 2 , a step in phase is taken where the deficit is made up instantaneously. The output frequency is then a steady carrier which has been phase modulated by a sawtooth signal (see Figure 5). The period of the sawtooth phase modulation is the time required to accumulate a 2 difference in phase between the required average frequency and one quarter of the clock frequency. The amplitude of the sawtooth phase modulation is 2 .
Figure 3. Integrator Output for lIN = 250 µA
put change is observed for a very small increase in the input current. The output frequency continues to run at one quarter of the clock, delivering an average of 250 µA to the summing junction. Since the input current is slightly larger than this, charge accumulates in the integrator and the sawtooth signal starts to drift downward. As the integrator sawtooth drifts down, the comparator threshold is crossed earlier and earlier in each sucREV. A 5
Figure 5. Phase Modulation
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