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Details, datasheet, quote on part number:AD667SD
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| Part: | AD667SD |
| Category: | Data Conversion => DAC (Digital to Analog Converters) => 10-14 bit |
| Description: | Microprocessor-compatible 12-Bit D/A Converter |
| Company: | Analog Devices |
| Datasheet: | Download AD667SD datasheet File size : 336 kB |
| Request For quote: | Find where to buy AD667SD
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Datasheet text preview:
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FEATURES Complete 12-Bit D/A Function Double-Buffered Latch On Chip Output Amplifier High Stability Buried Zener Reference Single Chip Construction Monotonicity Guaranteed Over Temperature Linearity Guaranteed Over Temperature: 1/2 LSB max Settling Time: 3 s max to 0.01% Guaranteed for Operation with 12 V or 15 V Supplies Low Power: 300 mW Including Reference TTL/5 V CMOS Compatible Logic Inputs Low Logic Input Currents MIL-STD-883 Compliant Versions Available PRODUCT DESCRIPTION
Microprocessor-Compatible 12-Bit D/A Converter AD667*
FUNCTIONAL BLOCK DIAGRAM
The AD667 is a complete voltage output 12-bit digital-to-analog converter including a high stability buried Zener voltage reference and double-buffered input latch on a single chip. The converter uses 12 precision high speed bipolar current steering switches and a laser trimmed thin-film resistor network to provide fast settling time and high accuracy. Microprocessor compatibility is achieved by the on-chip doublebuffered latch. The design of the input latch allows direct interface to 4-, 8-, 12-, or 16-bit buses. The 12 bits of data from the first rank of latches can then be transferred to the second rank, avoiding generation of spurious analog output values. The latch responds to strobe pulses as short as 100 ns, allowing use with the fastest available microprocessors. The functional completeness and high performance in the AD667 results from a combination of advanced switch design, high speed bipolar manufacturing process, and the proven laser wafer-trimming (LWT) technology. The AD667 is trimmed at the wafer level and is specified to ± 1/4 LSB maximum linearity error (K, B grades) at +25°C and ± 1/2 LSB over the full operating temperature range. The subsurface (buried) Zener diode on the chip provides a low noise voltage reference which has long-term stability and temperature drift characteristics comparable to the best discrete reference diodes. The laser trimming process which provides the excellent linearity, is also used to trim the absolute value of the reference as well as its temperature coefficient. The AD667 is thus well suited for wide temperature range performance with ± 1/2 LSB maximum linearity error and guaranteed monotonicity over the full temperature range. Typical full-scale gain TC is 5 ppm/°C.
*Protected by Patent Numbers 3,803,590; 3,890,611; 3,932,863; 3,978,473; 4,020,486; and others pending.
The AD667 is available in five performance grades. The AD667J and K are specified for use over the 0°C to +70°C temperature range and are available in a 28-pin molded plastic DIP (N) or PLCC (P) package. The AD667S grade is specified for the 55°C to +125°C range and is available in the ceramic DIP (D) or LCC (E) package. The AD667A and B are specified for use over the 25°C to +85°C temperature range and are available in a 28-pin hermetically sealed ceramic DIP (D) package.
PRODUCT HIGHLIGHTS
1. The AD667 is a complete voltage output DAC with voltage reference and digital latches on a single IC chip. 2. The double-buffered latch structure permits direct interface to 4-, 8-, 12-, or 16-bit data buses. All logic inputs are TTL or 5 volt CMOS compatible. 3. The internal buried Zener reference is laser-trimmed to 10.00 volts with a ± 1% maximum error. The reference voltage is also available for external application. 4. The gain setting and bipolar offset resistors are matched to the internal ladder network to guarantee a low gain temperature coefficient and are laser-trimmed for minimum full-scale and bipolar offset errors. 5. The precision high speed current steering switch and on-board high speed output amplifier settle within 1/2 LSB for a 10 V full-scale transition in 2.0 µs as when properly compensated. 6. The AD667 is available in versions compliant with MILSTD-883. Refer to the Analog Devices Military Products Databook or current AD667/883B data sheet for detailed specifications.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD667SPECIFICATIONS
Model Min DIGITAL INPUTS Resolution Logic Levels (TTL, Compatible, T MINTMAX)1 VIH (Logic "l'') VIL (Logic "0") IIH (VIH = 5.5 V) IIL (VIL = 0.8 V) TRANSFER CHARACTERISTICS ACCURACY Linearity Error @ +25°C TA = TMIN to TMAX Differential Linearity Error @ +25°C TA = TMIN to TMAX Gain Error 2 Unipolar Offset Error 2 Bipolar Zero 2 DRIFT Differential Linearity Gain (Full Scale) T A = 25°C to TMIN or TMAX Unipolar Offset T A = 25°C to TMIN or TMAX Bipolar Zero T A = 25°C to TMIN or TMAX CONVERSION SPEED Settling Time to ± 0.01% of FSR for FSR Change (2 k 500 pF Load) with 10 k Feedback with 5 k Feedback For LSB Change Slew Rate ANALOG OUTPUT Ranges 4 Output Current Output Impedance (DC) Short Circuit Current REFERENCE OUTPUT External Current POWER SUPPLY SENSITIVITY VCC = +11.4 V to +16.5 V dc VEE = 11.4 V to 16.5 V dc POWER SUPPLY REQUIREMENTS Rated Voltages Range 4 Supply Current +11.4 V to +16.5 V dc 11.4 V to 16.5 V dc TEMPERATURE RANGE Specification Storage NOTES
1
2
(@ TA = +25 C,
AD667J Typ
12 V,
Max
15 V power supplies unless otherwise noted)
Min AD667K Typ Max Units
12 +2.0 0 3 1 +5.5 +0.8 10 5 +2.0 0 3 1
12 +5.5 +0.8 10 5
Bits V V µA µA
+ 1/4 1/2 ± 1/2 3/4 ± 1/2 3/4 Monotonicity Guaranteed ± 0.1 0.2 ±1 2 ± 0.05 0.1 ±2 ±5 ±1 ±5
± 1/8 1/4 ± 1/4 1/2 ± 1/4 1/2 Monotonicity Guaranteed ± 0.1 0.2 ±1 2 ± 0.05 0.1 ±2 ±5
LSB LSB LSB LSB % FSR3 LSB % of FSR ppm of FSR/°C ppm of FSR/°C ppm of FSR/°C ppm of FSR/°C
± 30 ±3 ± 10
± 15 ±3 ± 10
3 2 1 10 ± 2.5, ± 5, ± 10, +5, +10 0.05
4 3 10
3 2 1
4 3
µs µs µs V/µs V mA mA V mA ppm of FS/% ppm of FS/% V V mA mA °C °C
±5
±5 40
± 2.5, ± 5, ± 10, +5, +10 0.05 40
9.90 0.1
10.00 1.0 5 5 ± 12, ± 15
10.10
9.90 0.1
10.00 1.0 5 5 ± 12, ± 15
10.10
10 10
10 10
11.4
16.5 12 25 +70 +125
11.4
16.5 12 25 +70 +125
8 20 0 65
8 20 0 65
The digital input specifications are 100% tested at +25°C, and guaranteed but not tested over the full temperature range. Adjustable to zero. 3 FSR means "Full-Scale Range" and is 20 V for ± 10 V range and 10 V for the ± 5 V range. 4 A minimum power supply of ± 12.5 V is required for a ± 10 V full-scale output and ± 11.4 V is required for all other voltage ranges. Specifications subject to change without notice. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
ABSOLUTE MAXIMUM RATINGS
TIMING SPECIFICATIONS
(All Models, T A = +25°C, VCC = +12 V or +15 V, V EE = 12 V or 15 V)
Symbol t DC t AC t CP t DH t SETT
Parameter Data Valid to End of CS Address Valid to End of CS CS Pulse Width Data Hold Time Output Voltage Settling Time
Min 50 100 100 0
Typ _ 2
Max _ 4 ns ns ns ns µs
VCC to Power Ground . . . . . . . . . . . . . . . . . . . . . 0 V to +18 V VEE to Power Ground . . . . . . . . . . . . . . . . . . . . . 0 V to 18 V Digital Inputs (Pins 1115, 1728) to Power Ground . . . . . . . . . . . . . . . . . . . . 1.0 V to +7.0 V Ref In to Reference Ground . . . . . . . . . . . . . . . . . . . . . . ± 12 V Bipolar Offset to Reference Ground . . . . . . . . . . . . . . . . ± 12 V 10 V Span R to Reference Ground . . . . . . . . . . . . . . . . . ± 12 V 20 V Span R to Reference Ground . . . . . . . . . . . . . . . . . ± 24 V Ref Out, VOUT (Pins 6, 9) . . Indefinite Short to Power Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . Momentary Short to VCC Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
2
REV. A
AD667
Model Min DIGITAL INPUTS Resolution Logic Levels (TTL, Compatible, TMINTMAX)1 VIH (Logic "l'') VIL (Logic "0") IIH (VIH = 5.5 V) IIL (VIL = 0.8 V) TRANSFER CHARACTERISTICS ACCURACY Linearity Error @ +25°C TA = TMIN to TMAX Differential Linearity Error @ +25°C TA = TMIN to TMAX Gain Error2 Unipolar Offset Error 2 Bipolar Zero2 DRIFT Differential Linearity Gain (Full Scale) TA = 25°C to TMIN or TMAX Unipolar Offset TA = 25°C to TMIN or TMAX Bipolar Zero T A = 25°C to TMIN or T MAX CONVERSION SPEED Settling Time to ± 0.01% of FSR for FSR Change (2 k 500 pF Load) with 10 k Feedback with 5 k Feedback For LSB Change Slew Rate ANALOG OUTPUT Ranges 4 Output Current Output Impedance (DC) Short Circuit Current REFERENCE OUTPUT External Current POWER SUPPLY SENSITIVITY VCC = +11.4 V to +16.5 V dc VEE = 11.4 V to 16.5 V dc POWER SUPPLY REQUIREMENTS Rated Voltages Range 4 Supply Current +11.4 V to +16.5 V dc 11.4 V to 16.5 V dc TEMPERATURE RANGE Specification Storage ±5 AD667A Typ Max Min AD667B Typ Max Min AD667S Typ Max Units
12 +2.0 0 3 1 +5.5 +0.8 10 5 +2.0 0 3 1
12 +5.5 +0.8 10 5 +2.0 0 3 1
12 +5.5 +0.7 10 5
Bits V V µA µA
+ 1/4 1/2 ± 1/2 3/4 ± 1/2 3/4 Monotonicity Guaranteed ± 0.1 0.2 ±1 2 ± 0.05 0.1 ±2 ±5 ±1 ±5
± 1/8 1/4 ± 1/4 1/2 ± 1/4 1/2 Monotonicity Guaranteed ± 0.1 0.2 ±1 2 ± 0.05 0.1 ±2 ±5
± 1/8 1/2 ± 1/8 3/4 ± 1/4 3/4 Monotonicity Guaranteed ± 0.1 0.2 ±1 2 ± 0.05 0.1 ±2 ± 15
LSB LSB LSB LSB % FSR3 LSB % of FSR ppm of FSR/°C ppm of FSR/°C ppm of FSR/°C ppm of FSR/°C
± 30 ±3 ± 10
± 15 ±3 ± 10
30 3 10
3 2 1 10
4 3 10
3 2 1
4 3 10
3 2 1
4 3
µs µs µs V/µs V mA mA V mA ppm of FS/% ppm of FS/% V V mA mA °C °C
± 2.5, ± 5, ± 10, +5, +10 0.05 40
±5
± 2.5, ± 5, ± 10, +5, +10 0.05 40
±5
± 2.5, ± 5, ± 10, +5, +10 0.05 40
9.90 0.1
10.00 1.0 5 5 ± 12, ± 15
10.10
9.90 0.1
10.00 1.0 5 5 ± 12, ± 15
10.10
9.90 1.0
10.00
10.10
10 10
10 10
5 5 ± 12, ± 15
10 10
11.4
16.5 12 25 +85 +150
11.4
16.5 12 25 +85 +150
11.4
16.5 12 25 +125 +150
8 20 25 65
8 20 25 65
8 20 55 65
TIMING DIAGRAMS WRITE CYCLE #1
WRITE CYCLE #2
(Load Second Rank from First Rank; A2, A1, A0 = 1)
(Load First Rank from Data Bus; A3 = 1)
REV. A
3
AD667
PIN CONNECTIONS PLCC, LCC DIP
ORDERING GUIDE
Temperature Range-- C 0 to +70 0 to +70 0 to +70 0 to +70 25 to +85 25 to +85 55 to +125 55 to +125 55 to +125 Linearity Gain Error Max TC Max @ +25 C ppm/ C Package Option2 ± 1/2 LSB ± 1/2 LSB ± 1/4 LSB ± 1/4 LSB ± 1/2 LSB ± 1/4 LSB ± 1/2 LSB ± 1/2 LSB * 30 30 15 15 30 15 30 30 * Plastic DIP (N-28) PLCC (P-28A) Plastic DIP (N-28) PLCC (P-28A) Ceramic DIP (D-28) Ceramic DIP (D-28) Ceramic DIP (D-28) LCC (E-28A) *
Model l AD667JN AD667JP AD667KN AD667KP AD667AD AD667BD AD667SD AD667SE AD667/883B
from the ideal analog output (a straight line drawn from 0 to FS 1 LSB) for any bit combination. The AD667 is laser trimmed to 1/4 LSB (0.006% of FS) maximum error at +25°C for the K and B versions and 1/2 LSB for the J, A and S versions. MONOTONICITY: A DAC is said to be monotonic if the output either increases or remains constant for increasing digital inputs such that the output will always be a nondecreasing function of input. All versions of the AD667 are monotonic over their full operating temperature range. DIFFERENTIAL NONLINEARITY: Monotonic behavior requires that the differential linearity error be less than 1 LSB both at +25°C and over the temperature range of interest. Differential nonlinearity is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. For example, for a 10 volt full-scale output, a change of 1 LSB in digital input code should result in a 2.44 mV change in the analog output (1 LSB = 10 V × 1/4096 = 2.44 mV). If in actual use, however, a 1 LSB change in the input code results in a change of only 0.61 mV (1/4 LSB) in analog output, the differential linearity error would be 1.83 mV, or 3/4 LSB. The AD667K and B grades have a max differential linearity error of 1/2 LSB, which specifies that every step will be at least 1/2 LSB and at most 1 1/2 LSB.
NOTES *Refer to AD667/883B military data sheet. 1 For details on grade and package offerings screened in accordance with MIL-STD883, refer to the Analog Devices Military Products Databook or current AD667/ 883B data sheet. 2 D = Ceramic DIP; E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip.
THE AD667 OFFERS TRUE 12-BIT PERFORMANCE OVER THE FULL TEMPERATURE RANGE
LINEARITY ERROR: Analog Devices defines linearity error as the maximum deviation of the actual, adjusted DAC output
Table I. Output Voltage Range Connections
Output Range ± 10 V ±5 V ± 2.5 V 0 V to +10 V 0 V to +5 V
Digital Input Codes Offset Binary Offset Binary Offset Binary Straight Binary Straight Binary
Connect Pin 9 to 1 1 and 2 2 1 and 2 2
Connect Pin 1 to 9 2 and 9 3 2 and 9 3
Connect Pin 2 to NC 1 and 9 9 1 and 9 9 4
Connect Pin 4 to 6 (Through 50 Fixed or 100 Trim Resistor) 6 (Through 50 Fixed or 100 Trim Resistor) 6 (Through 50 Fixed or 100 Trim Resistor) 5 (or Optional Trim--See Figure 2) 5 (or Optional Trim--See Figure 2) REV. A
AD667
ANALOG CIRCUIT CONNECTIONS
Internal scaling resistors provided in the AD667 may be connected to produce bipolar output voltage ranges of ±10, ±5 or ±2.5 V or unipolar output voltage ranges of 0 V to +5 V or 0 V to +10 V. Gain and offset drift are minimized in the AD667 because of the thermal tracking of the scaling resistors with other device components. Connections for various output voltage ranges are shown in Table I.
Figure 3. ± 5 V Bipolar Voltage Output
INTERNAL/EXTERNAL REFERENCE USE
Figure 1. Output Amplifier Voltage Range Scaling Circuit
UNIPOLAR CONFIGURATION (Figure 2)
This configuration will provide a unipolar 0 volt to +10 volt output range. In this mode, the bipolar offset terminal, Pin 4, should be grounded if not used for trimming.
The AD667 has an internal low noise buried Zener diode reference which is trimmed for absolute accuracy and temperature coefficient. This reference is buffered and optimized for use in a high speed DAC and will give long-term stability equal or superior to the best discrete Zener reference diodes. The performance of the AD667 is specified with the internal reference driving the DAC since all trimming and testing (especially for full-scale error and bipolar offset) is done in this configuration. The internal reference has sufficient buffering to drive external circuitry in addition to the reference currents required for the DAC (typically 0. 5 mA to Ref In and 1.0 mA to Bipolar Offset). A minimum of 0.1 mA is available for driving external loads. The AD667 reference output should be buffered with an external op amp if it is required to supply more than 0.1 mA output current. The reference is typically trimmed to ± 0.2%, then tested and guaranteed to ± 1.0% max error. The temperature coefficient is comparable to that of the full-scale TC for a particular grade. If an external reference is used (10.000 V, for example), additional trim range must be provided, since the internal reference has a tolerance of ± 1%, and the AD667 full-scale and bipolar offset are both trimmed with the internal reference. The gain and offset trim resistors give about ± 0.25% adjustment range, which is sufficient for the AD667 when used with the internal reference. It is also possible to use external references other than 10 volts. The recommended range of reference voltage is from +8 to +11 volts, which allows both 8.192 V and 10.24 V ranges to be used. The AD667 is optimized for fixed-reference applications. If the reference voltage is expected to vary over a wide range in a particular application, a CMOS multiplying DAC is a better choice. Reduced values of reference voltage will also permit the ± 12 volt ± 5% power supply requirement to be relaxed to ± 12 volts ± 10%. It is not recommended that the AD667 be used with external feedback resistors to modify the scale factor. The internal resistors are trimmed to ratio-match and temperature-track the other resistors on the chip, even though their absolute tolerances are ± 20%, and absolute temperature coefficients are approximately 50 ppm/°C. If external resistors are used, a wide trim range (± 20%) will be needed and temperature drift will be increased to reflect the mismatch between the temperature coefficients of the internal and external resistors. 5
Figure 2. 0 V to +10 V Unipolar Voltage Output
STEP I . . . ZERO ADJUST Turn all bits OFF and adjust zero trimmer R1, until the output reads 0.000 volts (1 LSB = 2.44 mV). In most cases this trim is not needed, and Pin 4 should be connected to Pin 5. STEP II . . . GAIN ADJUST Turn all bits ON and adjust 100 gain trimmer R2, until the output is 9.9976 volts. (Full scale is adjusted to 1 LSB less than nominal full scale of 10.000 volts.)
BIPOLAR CONFIGURATION (Figure 3)
This configuration will provide a bipolar output voltage from 5.000 to +4.9976 volts, with positive full scale occurring with all bits ON (all 1s). STEP I . . . OFFSET ADJUST Turn OFF all bits. Adjust 100 trimmer R1 to give 5.000 volts output. STEP II . . . GAIN ADJUST Turn ON all bits. Adjust 100 gain trimmer R2 to give a reading of +4.9976 volts. REV. A
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