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Details, datasheet, quote on part number:AD669BN
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Datasheet text preview:
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FEATURES Complete 16-Bit D/A Function On-Chip Output Amplifier High Stability Buried Zener Reference Monolithic BiMOS II Construction 1 LSB Integral Linearity Error 15-Bit Monotonic over Temperature Microprocessor Compatible 16-Bit Parallel Input Double-Buffered Latches Fast 40 ns Write Pulse Unipolar or Bipolar Output Low Glitch: 15 nV-s Low THD+N: 0.009% MIL-STD-883 Compliant Versions Available
(MSB) DB15 7 CS 6 L1 5 LDAC 23 10k REF IN REF OUT 27 28
Monolithic 16-Bit DACPORT AD669
FUNCTIONAL BLOCK DIAGRAM
(LSB) DB0 22 10k 10.05k
16-BIT LATCH
26 SPAN/ BIP OFF
16-BIT LATCH 16-BIT DAC
AMP
25 VOUT 24 AGND
10V REF 1 V EE 2 +VCC
AD669
3 +VLL 4 DGND
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD669 DACPORT® is a complete 16-bit monolithic D/A converter with an on-board reference and output amplifier. It is manufactured on Analog Devices' BiMOS II process. This process allows the fabrication of low power CMOS logic functions on the same chip as high precision bipolar linear circuitry. The AD669 chip includes current switches, decoding logic, an output amplifier, a buried Zener reference and double-buffered latches. The AD669's architecture insures 15-bit monotonicity over temperature. Integral nonlinearity is maintained at ± 0.003%, while differential nonlinearity is ± 0.003% max. The on-chip output amplifier provides a voltage output settling time of 10 µs to within 1/2 LSB for a full-scale step. Data is loaded into the AD669 in a parallel 16-bit format. The double-buffered latch structure eliminates data skew errors and provides for simultaneous updating of DACs in a multi-DAC system. Three TTL/LSTTL/5 V CMOS compatible signals control the latches: CS, L1 and LDAC. The output range of the AD669 is pin programmable and can be set to provide a unipolar output range of 0 V to +10 V or a bipolar output range of 10 V to +10 V. The AD669 is available in seven grades: AN and BN versions are specified from 40°C to +85°C and are packaged in a 28-pin plastic DIP. The AR and BR versions are specified for 40°C to +85°C operation and are packaged in a 28-pin SOIC. The SQ version is specified from 55°C to +125°C and is packaged in a hermetic 28-pin cerdip package. The AD669 is also available compliant to MIL-STD-883. Refer to the AD669/883B data sheet for specifications and test conditions.
DACPORT is a registered trademark of Analog Devices, Inc.
1. The AD669 is a complete voltage output 16-bit DAC with voltage reference and digital latches on a single IC chip. 2. The internal buried Zener reference is laser trimmed to 10.000 volts with a ± 0.2% maximum error. The reference voltage is also available for external applications. 3. The AD669 is both dc and ac specified. DC specs include ± 1 LSB INL error and ± 1 LSB DNL error. AC specs include 0.009% THD+ N and 83 dB SNR. The ac specifications make the AD669 suitable for signal generation applications. 4. The double-buffered latches on the AD669 eliminate data skew errors while allowing simultaneous updating of DACs in multi-DAC systems. 5. The output range is a pin-programmable unipolar 0 V to +10 V or bipolar 10 V to +10 V output. No external components are necessary to set the desired output range. 6. The AD669 is available in versions compliant with MILSTD-883. Refer to the Analog Devices Military Products Databook or current AD669/883B data sheet for detailed specifications.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD669SPECIFICATIONS (@ T = +25 C, V
A
CC
= +15 V, VEE = 15 V, VLL = +5 V, unless otherwise noted)
AD669AQ/SQ Min Typ Max 16 5.5 0.8 10 10 2 4 2 4 * * * * * * * * * * 14 0.15 25 5 5 15 12 0.10 15 5 3 15 10 * * * * 1000 * * * * * * * * * * 15 * * * * * * * * * 15 0.10 15 2.5 3 10 5 * * * 15 AD669BN/BQ/BR Min Typ Max 16 * * * * * * 1 2 1 2 Units Bits Volts Volts µA µA LSB LSB LSB LSB Bits % of FSR ppm/°C mV ppm/°C mV ppm/°C k k Volts ppm/°C mA pF mA
Model RESOLUTION DIGITAL INPUTS (TMIN to TMAX) VIH (Logic "1" ) VIL (Logic "0" ) IIH (VIH = 5.5 V) IIL (VIL = 0 V) TRANSFER FUNCTION CHARACTERISTICS1 Integral Nonlinearity TMIN to TMAX Differential Nonlinearity TMIN to TMAX Monotonicity Over Temperature Gain Error2, 5 Gain Drift2 (TMIN to TMAX) Unipolar Offset Unipolar Offset Drift (TMIN to TMAX) Bipolar Zero Error Bipolar Zero Error Drift (TMIN to TMAX) REFERENCE INPUT Input Resistance Bipolar Offset Input Resistance REFERENCE OUTPUT Voltage Drift External Current3 Capacitive Load Short Circuit Current OUTPUT CHARACTERISTICS Output Voltage Range Unipolar Configuration Bipolar Configuration Output Current Capacitive Load Short Circuit Current POWER SUPPLIES Voltage VC C 4 VE E 4 VL L Current (No Load) ICC IEE ILL @ VIH, VIL = 5, 0 V @ VIH, VIL = 2.4, 0.4 V Power Supply Sensitivity Power Dissipation (Static, No Load) TEMPERATURE RANGE Specified Performance (A, B) Specified Performance (S)
AD669AN/AR Min Typ Max 16 2.0 0
14
7 7 9.98 2
10 10 10.00 4 25
13 13 10.02 25
0 10 5 25
+10 +10 1000
* * * *
* * *
* * * *
* * *
Volts Volts mA pF mA
+13.5 13.5 +4.5 +12 12 0.3 3 1 365 40
+16.5 16.5 +5.5 +18 18 2 7.5 3 625 +85
* * * * * * * * * 40 55
* * * * * * * *
* * * * * * * * * 40
* * * * * * * *
Volts Volts Volts mA mA mA mA ppm/% mW °C °C
+85 +125
+85
NOTES 1 For 16-bit resolution, 1 LSB = 0.0015% of FSR = 15 ppm of FSR. For 15-bit resolution, 1 LSB = 0.003% of FSR = 30 ppm of FSR. For 14-bit resolution 1 LSB = 0.006% of FSR = 60 ppm of FSR. FSR stands for Full-Scale Range and is 10 V for a 0 V to + 10 V span and 20 V for a 10 V to +10 V span. 2 Gain error and gain drift measured using the internal reference. Gain drift is primarily reference related. See the Using the AD669 with the AD688 Reference section for further information. 3 External current is defined as the current available in addition to that supplied to REF IN and SPAN/BIPOLAR OFFSET on the AD669. 4 Operation on ± 12 V supplies is possible using an external reference like the AD586 and reducing the output range. Refer to the Internal/External Reference Use section. 5 Measured with fixed 50 resistors. Eliminating these resistors increases the gain error by 0.25% of FSR (Unipolar mode) or 0.50% of FSR (Bipolar mode). Refer to the Analog Circuit Connections section. *Same as AD669AN/AR specification. Specifications subject to change without notice. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed. Those shown in boldface are tested on all production units.
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AD669 AC PERFORMANCE CHARACTERISTICS
Parameter Output Settling Time (Time to ± 0.0008% FS with 2 k, 1000 pF Load) Limit 13 8 10 6 8 2.5 0.009 0.07 7.0 83 15 2 120 125
(With the exception of Total Harmonic Distortion + Noise and Signal-to-Noise Ratio, these characteristics are included for design guidance only and are not subject to test. THD+N and SNR are 100% tested. TMIN TA TMAX, VCC = +15 V, VEE = 15 V, VLL = +5 V except where noted.)
Units µs max µs typ µs typ µs typ µs typ µs typ % max % max % max dB min nV-s typ nV-s typ nV/Hz typ nV/Hz typ Test Conditions/Comments 20 V Step, TA = +25°C 20 V Step, TA = +25°C 20 V Step, TMIN TA TMAX 10 V Step, TA = +25°C 10 V Step, TMIN TA TMAX 1 LSB Step, TMIN TA TMAX 0 dB, 1001 Hz; Sample Rate = 100 kHz; TA = +25°C 20 dB, 1001 Hz; Sample Rate = 100 kHz; TA = +25°C 60 dB, 1001 Hz; Sample Rate = 100 kHz; TA = +25°C TA = +25°C DAC Alternately Loaded with 8000H and 7FFFH DAC Alternately Loaded with 0000H and FFFFH; CS High Measured at VOUT, 20 V Span; Excludes Reference Measured at REF OUT
Total Harmonic Distortion + Noise A, B, S Grade A, B, S Grade A, B, S Grade Signal-to-Noise Ratio Digital-to-Analog Glitch Impulse Digital Feedthrough Output Noise Voltage Density (1 kHz 1 MHz) Reference Noise
Specifications subject to change without notice. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed. Those shown in boldface are tested on all production units.
TIMING CHARACTERISTICS
VCC = +15 V, VEE = 15 V, VLL = +5 V, VHI = 2.4 V, VLO = 0.4 V Limit Limit Limit 40 C to 55 C to Parameter +25 C +85 C +125 C Units
(Figure la) tCS tLI tDS t DH tLH tLW (Figure lb) tLOW tHIGH tDS tDH 40 40 30 10 90 40 130 40 120 10 50 50 35 10 110 45 150 45 140 10 55 55 40 15 120 45 165 45 150 15 ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min
CS L1
tCS tL1
DATA
LDAC
t DS
t DH t LH t LW
Figure 1a. AD669 Level Triggered Timing Diagram
t LOW
CS AND/OR L1, LDAC DATA
t HIGH
Specifications subject to change without notice. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed. Those shown in boldface are tested on all production units.
t DS t DH
TIE CS AND/OR L1 TO GROUND OR TOGETHER WITH LDAC
Figure 1b. AD669 Edge Triggered Timing Diagram
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AD669
ESD SENSITIVITY
The AD669 features input protection circuitry consisting of large transistors and polysilicon series resistors to dissipate both high-energy discharges (Human Body Model) and fast, low-energy pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-883: C, the AD669 has been classified as a Class 2 device. Proper ESD precautions are strongly recommended to avoid functional damage or performance degradation. Charges as high as 4000 volts readily accumulate on the human body and test equipment and discharge without detection. Unused devices must be stored in conductive foam or shunts, and the foam should be discharged to the destination socket before devices are removed. For further information on ESD precautions, refer to Analog Devices' ESD Prevention Manual.
ABSOLUTE MAXIMUM RATINGS *
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION
VEE VCC VLL DGND L1 CS DB15 DB14 DB13 1 2 3 4 5 6 7 8 9 28 27 26 25 24 23 REF OUT REF IN SPAN/BIP OFFSET VOUT AGND LDAC DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7
VCC to AGND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +17.0 V VEE to AGND . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to 17.0 V VLL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 1 V Digital Inputs (Pins 5 through 23) to DGND . . . . . . 1.0 V to . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0 V REF IN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 10.5 V Span/Bipolar Offset to AGND . . . . . . . . . . . . . . . . . . . ± 10.5 V REF OUT, VOUT . . . . . . Indefinite Short To AGND, DGND, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC, VEE, and VLL Power Dissipation (Any Package) To +60°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW Derates above +60°C . . . . . . . . . . . . . . . . . . . . . .8.7 mW/°C Storage Temperature . . . . . . . . . . . . . . . . . . . 65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indi cated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
AD669
TOP VIEW (Not to Scale)
22 21 20 19 18 17 16 15
DB12 10 DB11 11 DB10 12 DB9 13 DB8 14
ORDERING GUIDE
Model AD669AN AD669AR AD669BN AD669BR AD669AQ AD669BQ AD669SQ AD669/883B**
Temperature Range 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C 55°C to +125°C 55°C to +125°C
Linearity Error Max TMINTMAX ± 4 LSB ± 4 LSB ± 2 LSB ± 2 LSB ± 4 LSB ± 2 LSB ± 4 LSB **
Gain TC max ppm/ C 25 25 15 15 15 15 15 **
Package Description Plastic DIP SOIC Plastic DIP SOIC Cerdip Cerdip Cerdip **
Package Option* N-28 R-28 N-28 R-28 Q-28 Q-28 Q-28 **
** N = Plastic DIP; Q = Cerdip; R = SOIC. ** Refer to AD669/883B military data sheet.
10 60dB 1
THD + N %
10 60dB 1
THD + N %
0.1
0.1
20dB
20dB
0.01 0dB
0.01 0dB 0.001 50 25 75 0 25 50 TEMPERATURE °C 100 125
0.001 100 1000 FREQUENCY Hz 10000
THD+N vs. Temperature
THD+N vs. Frequency
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AD669
DEFINITIONS OF SPECIFICATIONS THEORY OF OPERATION
INTEGRAL NONLINEARITY: Analog Devices defines integral nonlinearity as the maximum deviation of the actual, adjusted DAC output from the ideal analog output (a straight line drawn from 0 to FS1 LSB) for any bit combination. This is also referred to as relative accuracy. DIFFERENTIAL NONLINEARITY: Differential nonlinearity is the measure of the change in the analog output, normalized to full scale, associated with a 1 LSB change in the digital input code. Monotonic behavior requires that the differential linearity error be within ± 1 LSB over the temperature range of interest. MONOTONICITY: A DAC is monotonic if the output either increases or remains constant for increasing digital inputs with the result that the output will always be a single-valued function of the input. GAIN ERROR: Gain error is a measure of the output error between an ideal DAC and the actual device output with all 1s loaded after offset error has been adjusted out. OFFSET ERROR: Offset error is a combination of the offset errors of the voltage-mode DAC and the output amplifier and is measured with all 0s loaded in the DAC. BIPOLAR ZERO ERROR: When the AD669 is connected for bipolar output and 10 . . . 000 is loaded in the DAC, the deviation of the analog output from the ideal midscale value of 0 V is called the bipolar zero error. DRIFT: Drift is the change in a parameter (such as gain, offset and bipolar zero) over a specified temperature range. The drift temperature coefficient, specified in ppm/°C, is calculated by measuring the parameter at TMIN, 25°C and TMAX and dividing the change in the parameter by the corresponding temperature change. TOTAL HARMONIC DISTORTION + NOISE: Total harmonic distortion + noise (THD+N) is defined as the ratio of the square root of the sum of the squares of the values of the harmonics and noise to the value of the fundamental input frequency. It is usually expressed in percent (%). THD+N is a measure of the magnitude and distribution of linearity error, differential linearity error, quantization error and noise. The distribution of these errors may be different, depending upon the amplitude of the output signal. Therefore, to be the most useful, THD+N should be specified for both large and small signal amplitudes. SIGNAL-TO-NOISE RATIO: The signal-to-noise ratio is defined as the ratio of the amplitude of the output when a fullscale signal is present to the output with no signal present. This is measured in dB. DIGITAL-TO-ANALOG GLITCH IMPULSE: This is the amount of charge injected from the digital inputs to the analog output when the inputs change state. This is measured at half scale when the DAC switches around the MSB and as many as possible switches change state, i.e., from 011 . . . 111 to 100 . . . 000. DIGITAL FEEDTHROUGH: When the DAC is not selected (i.e., CS is held high), high frequency logic activity on the digital inputs is capacitively coupled through the device to show up as noise on the VOUT pin. This noise is digital feedthrough.
The AD669 uses an array of bipolar current sources with MOS current steering switches to develop a current proportional to the applied digital word, ranging from 0 mA to 2 mA. A segmented architecture is used, where the most significant four data bits are thermometer decoded to drive 15 equal current sources. The lesser bits are scaled using a R-2R ladder, then applied together with the segmented sources to the summing node of the output amplifier. The internal span/bipolar offset resistor can be connected to the DAC output to provide a 0 V to +10 V span, or it can be connected to the reference input to provide a 10 V to +10 V span.
(MSB) DB15 7 CS L1 6 5 16-BIT LATCH 10k REF IN REF OUT 27 28 16-BIT DAC AMP 25 VOUT 24 AGND 10.05k 16-BIT LATCH (LSB) DB0 22 10k 26 SPAN/ BIP OFF
LDAC 23
10V REF 1 VEE 2 +VCC
AD669
3 +VLL 4 DGND
Figure 2. AD669 Functional Block Diagram
ANALOG CIRCUIT CONNECTIONS
Internal scaling resistors provided in the AD669 may be connected to produce a unipolar output range of 0 V to +10 V or a bipolar output range of 10 V to +10 V. Gain and offset drift are minimized in the AD669 because of the thermal tracking of the scaling resistors with other device components.
UNIPOLAR CONFIGURATION
The configuration shown in Figure 3a will provide a unipolar 0 V to +10 V output range. In this mode, 50 resistors are tied between the span/bipolar offset terminal (Pin 26) and VOUT (Pin 25), and between REF OUT (Pin 28) and REF IN (Pin 27). It is possible to use the AD669 without any external components by tying Pin 28 directly to Pin 27 and Pin 26 directly to Pin 25. Eliminating these resistors will increase the gain error by 0.25% of FSR.
(MSB) DB15 7 CS L1 6 5 16-BIT LATCH 10k 27 R1 50 28 16-BIT DAC AMP 25 R 10.05k 16-BIT LATCH (LSB) DB0 22 10k 26 2 50 OUTPUT
LDAC 23
10V REF 2 +VCC
AD669
3 +VLL 4
24
GND
1 V EE
Figure 3a. 0 V to +10 V Unipolar Voltage Output
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