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Details, datasheet, quote on part number:AD7008JP50
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| Part: | AD7008JP50 |
| Category: | Communication => Modems => Low-speed Modems |
| Description: | Numerically Controlled Oscillator Employing a 32-Bit Phase Accumulator, Sine And Cosine Look-up Tables And a 10-Bit DAC, CMOS |
| Company: | Analog Devices |
| Datasheet: | Download AD7008JP50 datasheet File size : 517 kB |
| Request For quote: | Find where to buy AD7008JP50
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Datasheet text preview:
a
FEATURES Single +5 V Supply 32-Bit Phase Accumulator On-Chip COSINE and SINE Look-Up Tables On-Chip 10-Bit DAC Frequency, Phase and Amplitude Modulation Parallel and Serial Loading Software and Hardware Power Down Options 20 MHz and 50 MHz Speed Grades 44-Pin PLCC APPLICATIONS Frequency Synthesizers Frequency, Phase or Amplitude Modulators DDS Tuning Digital Modulation
CMOS DDS Modulator AD7008
phase modulation, frequency modulation, and both in-phase and quadrature amplitude modulation suitable for QAM and SSB generation. Clock rates up to 20 MHz and 50 MHz are supported. Frequency accuracy can be controlled to one part in 4 billion. Modulation may be effected by loading registers either through the parallel microprocessor interface or the serial interface. A frequency-select pin permits selection between two frequencies on a per cycle basis. The serial and parallel interfaces may be operated independently and asynchronously from the DDS clock; the transfer control signals are internally synchronized to prevent metastability problems. The synchronizer can be bypassed to reduce the transfer latency in the event that the microprocessor clock is synchronous with the DDS clock. A power-down pin allows external control of a power-down mode (also accessible through the microprocessor interface) The AD7008 is available in 44-pin PLCC.
PRODUCT HIGHLIGHT
PRODUCT DESCRIPTION
The AD7008 direct digital synthesis chip is a numerically controlled oscillator employing a 32-bit phase accumulator, sine and cosine look-up tables and a 10-bit D/A converter integrated on a single CMOS chip. Modulation capabilities are provided for
1. Low Power 2. DSP/µP Interface 3. Completely Integrated
FUNCTIONAL BLOCK DIAGRAM
VAA CLOCK FSELECT FREQ0 REG 32 32 MUX 32 FREQ1 REG PHASE ACCUMULATOR 12 COS 10 PHASE REG SCLK SDATA 32-BIT SERIAL REGISTER IQMOD [9:0] 32 SIN 12 12 SIN/COS ROM 10 10 10 GND FS ADJUST VREF
IQMOD [19:10] 10 10 10 10-BIT DAC IOUT FULLSCALE ADJUST COMP
IOUT
AD7008
32-BIT PARALLEL REGISTER COMMAND REG
MPU INTERFACE
TRANSFER LOGIC
D0
D15
WR
CS
TC0
TC3
LOAD
TEST
RESET
SLEEP
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
V V = +5 V ± 5%; T = T to T AD7008SPECIFICATIONS1 I(OUT=and IOUT, unless otherwise noted) , R
AA DD A MIN MAX
SET
= 390 , RLOAD = 1 for
Test Conditions/ Comments
Parameter SIGNAL DAC SPECIFICATIONS Resolution Update Rate (fMAX) IOUT Full Scale Output Compliance DC Accuracy Integral Nonlinearity Differential Nonlinearity DDS SPECIFICATIONS 2 Update Rate (fMAX) Dynamic Specifications Signal-to-Noise Total Harmonic Distortion Spurious Free Dynamic Range (SFDR)3 Narrow Band (± 50 kHz) Wide Band (± 2 MHz) VOLTAGE REFERENCE Internal Reference @ +25°C4 Reference TC VREF Overdrive5 LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance POWER SUPPLIES V DD I AA I DD IAA + I DD fCLK = Max S l e e p = V DD NOTES
1 2 3
Min 10
AD7008AP20 Typ Max
Min 10
AD7008JP50 Typ
Max
Units Bits MSPS mA Volts LSB LSB
20 20 1 +1 ±1 20 50 55 50 53 +1 ±1 20
50 1
50
MSPS dB dB fCLK = fMAX, fOUT = 2 MHz fCLK = fMAX, fOUT = 2 MHz fCLK = 6.25 MHz, fOUT = 2.11 MHz
70 55 1.2 0 V DD 0 . 9 0.9 10 10 4.75 5.25 26 22 + 1.5/MHz 80 110 10 1.27 300 2 1.35
70 55 1.2 0 VDD 0 . 9 0.9 10 10 4.75 26 22 + 1.5/MHz 125 160 20 5.25 1.27 300 2 1.35
dBc dBc Volts ppm/°C V Volts Volts µA pF Volts mA mA mA mA
RSET = 390
Operating temperature ranges as follows: A Version: 40°C to +85°C; J Version: 0°C to +70°C. All dynamic specifications are measured using IOUT. 100% Production tested. fCLK = 6.25 MHz, Frequency Word = 5671C71C HEX, f OUT = 2.11 MHz. 4 VREF may be externally driven between 0 and V DD. 5 Do not allow reference current to cause power dissipation beyond the limit of I AA + IDD shown above. Specifications subject to change without notice.
2
REV. B
AD7008 TIMING CHARACTERISTICS (V
Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 Min 50 20 20 5 3 4t1 2t1 5 5 10 10 20 10 3 3 20 8 8 10 10 AD7008AP20 Typ Max
AA
= VDD +5 V ± 5%; TA = TMIN to TMAX, unless otherwise noted)
Min 20 8 8 5 3 4 t1 2 t1 5 5 10 10 20 10 3 3 20 8 8 10 10 AD7008JP50 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions/Comments CLOCK Period CLOCK High Duration CLOCK Low Duration CLOCK to Control Setup Time CLOCK to Control Hold Time LOAD Period LOAD High Duration1 LOAD High to TC0TC3 Setup Time LOAD High to TC0TC3 Hold Time WR Falling to CS Low Setup Time WR Falling to CS Low Hold Time Minimum WR Low Duration Minimum WR High Duration WR to D0D15 Setup Time WR to D0D15 Hold Time SCLK Period SCLK High Duration SCLK Low Duration SCLK Rising to SDATA Setup Time SCLK Rising to SDATA Hold Time
NOTE 1 May be reduced to 1t 1 if LOAD is synchronized to CLOCK and Setup (t 4) and Hold (t5) Times for LOAD to CLOCK are observed.
t1 t2
CLOCK
CS
t10
t11
t3 t4
FSEL, LOAD, TC3TC0 VALID VALID
WR
t12 t14
D0D15
t13
t15
t5
VALID DATA
Figure 1. Clock Synchronization Timing
Figure 3. Parallel Port Timing
t16
t6 t7
LOAD
SCLK
t17
t20
t18
t8
TC0TC3 VALID
t9
SDATA
t19
DB31 DB0
Figure 2. Register Transfer Timing
Figure 4. Serial Port Timing
REV. B
3
AD7008
ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise noted)
32-BIT PARALLEL ASSEMBLY REGISTER MSB A WORD LSB D15D0 A WORD*
VAA, VDD to GND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . 0.3 V to +0.3 V Digital I/O Voltage to DGND . . . . . . . . 0.3 V to VDD + 0.3 V Analog I/O Voltage to AGND . . . . . . . . 0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . . 40°C to +85°C Commercial (J Version) . . . . . . . . . . . . . . . . . .0°C to +70°C Storage Temperature Range . . . . . . . . . . . . . 65°C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +115°C PLCC JA Thermal Impedance . . . . . . . . . . . . . . . +53.8°C/W JC Thermal Impedance . . . . . . . . . . . . . . . +24.1°C/W
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
A WORD
B WORD
D15D0 B WORD
*MOST SIGNIFICANT WORD IS LOADED FIRST
Figure 5. 16-Bit Parallel Port Loading Sequence
32-BIT PARALLEL ASSEMBLY REGISTER MSB A BYTE LSB D7D0 A BYTE*
A BYTE
B BYTE
D7D0 B BYTE
A BYTE
B BYTE
C BYTE
D7D0 C BYTE
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
A BYTE
B BYTE
C BYTE
D BYTE
D7D0 D BYTE
*MOST SIGNIFICANT BYTE IS LOADED FIRST
AD7008AP20 40°C to +85°C AD7008JP50 0°C to +70°C AD7008/PCB*
44-Pin PLCC P-44A 44-Pin PLCC P-44A 13.5" Disk
Figure 6. 8-Bit Parallel Port Loading Sequence
*AD7008/PCB DDS Evaluation Kit, assembled and tested. Kit includes an AD7008JP50.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7008 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN CONFIGURATION PLCC
FS ADJUST SDATA
WARNING!
ESD SENSITIVE DEVICE
COMP
AGND
DGND
SCLK
6 DGND D8 D9 D10 D11 D12 D13 D14 D15 WR VDD 17 18 7 PIN NO. 1 IDENTIFIER
IOUT
IOUT
VREF
VAA
40 39 VDD RESET SLEEP LOAD
TEST
AD7008 PLCC
TOP VIEW (NOT TO SCALE)
TC3 TC2 TC1 TC0 FSELECT CLOCK 29 28 DGND
DGND
VDD
D1
D3
D5
D6
CS
D0
D2
D4
D7
4
REV. B
AD7008
PIN DESCRIPTION
Mnemonic
Function Positive power supply for the analog section. A 0.1 µF decoupling capacitor should be connected between VAA and AGND. This is +5 V ± 5%. Analog Ground. Positive power supply for the digital section. A 0.1 µF decoupling capacitor should be connected between VDD and DGND. This is +5 V ± 5%. Both VAA and VDD should be externally tied together. Digital Ground; both AGND and DGND should be externally tied together. Current Output. This is a high impedance current source. A load resistor should be connected between IOUT and AGND. IOUT should be either tied directly to AGND or through an external load resistor to AGND. Full-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND. This determines the magnitude of the full-scale DAC current. The relationship between RSET and the full-scale current is as follows: IOUTFULL-SCALE (mA) =
POWER SUPPLY V AA AGND VD D DGND IOUT, IOUT FS ADJUST
ANALOG SIGNAL AND REFERENCE
6233 × V REF RSET
VREF = 1.27 V nominal RSET = 390 typical
V REF
Voltage Reference Input. A 0.1 µF decoupling ceramic capacitor should be connected between VREF and VAA. There is an internal 1.27 volt reference which can be overdriven by an external reference if required. See specifications for maximum range. Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF decoupling ceramic capacitor should be connected between COMP and VAA. Digital Clock Input for DAC and NCO. DDS output frequencies are expressed as a binary fraction of the frequency of this clock. The output frequency accuracy and phase noise is determined by this clock. Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase accumulator. Frequency selection can be done on a cycle-per-cycle basis. See Tables I, II and III. Register load, active high digital Input. This pin, in conjunction with TC3TC0, control loading of internal registers from either the parallel or serial assembly registers. The load pin must be high at least 1t1. See Table II. Transfer Control address bus, digital inputs. This address determines the source and destination registers that are used during a transfer. The source register can either be the parallel assembly register or the serial assembly register. The destination register can be any of the following: COMMAND REG, FREQ0 REG, FREQ1 REG, PHASE REG or IQMOD REG. TC3TC0 should be valid prior to LOAD rising and should not change until LOAD falls. The Command Register can only be loaded from the parallel assembly register. See Table II. Chip Select, active low digital input. This input in conjunction with WR is used when writing to the parallel assembly register. Write, active low digital input. This input in conjunction with CS is used when writing to the parallel assembly register. Data Bus, digital inputs. These represent the low byte of the 16-bit data input port used to write to the 32-bit parallel assembly register. The databus can configured for either a 8-bit or 16-bit MPU/DSP ports. Data Bus, digital inputs. These represent the high byte of the 16-bit data input port used to write to the 32-bit parallel assembly register. The databus can be configured for either a 8-bit or 16-bit MPU/DSP ports. When the databus is configured for 8-bit operation, D8D15 should be tied to DGND. Serial Clock, digital input. SCLK is used, in conjunction with SDATA, to clock data into the 32-bit serial assembly register. Serial Data, digital input. Serial data is clocked on the rising edge of SCLK, Most Significant Bit (MSB) first. Low power sleep control, active high digital input. SLEEP puts the AD7008 into a low power sleep mode. Internal clocks are disabled, while also turning off the DAC current sources. A SLEEP bit is also provided in the COMMAND REG to put the AD7008 into a low power sleep mode. Register Reset, active high digital input. RESET clears the COMMAND REG and all the modulation registers to zero. Test Mode. This is used for factory test only and should be left as a No Connect. 5
COMP
DIGITAL INTERFACE AND CONTROL CLOCK FSELECT LOAD TC3TC0
CS WR D7D0 D15D8
SCLK SDATA SLEEP
RESET TEST REV. B
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