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Details, datasheet, quote on part number:AD7010ARS
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Datasheet text preview:
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FEATURES Single +5 V Supply On-Chip /4 DQPSK Modulator Root-Raised-Cosine Tx Filters, = 0.5 Two 10-Bit D/A Converters 4th Order Reconstruction Filters Differential Analog Outputs On-Chip Ramp Up/Down Power Control On-Chip Tx Offset Calibration Very Low Power Dissipation, 30 mW typ Power Down Mode < 5 A On-Chip Voltage Reference 24-Pin SSOP APPLICATIONS Japanese Digital Cellular Telephony
CMOS JDC /4 DQPSK Baseband Transmit Port AD7010
GENERAL DESCRIPTION
The AD7010 is a complete low power, CMOS, /4 DQPSK modulator with single +5 V power supply. The part is designed to perform the baseband conversion of I and Q transmit waveforms in accordance with the Japanese Digital Cellular Telephone system. The on-chip /4 Differential Quadrature Phase Shift Keying (DQPSK) digital modulator, which includes the Root Raised Cosine filters, generates I and Q data in response to the transmit data stream. The AD7010 also contains ramp control envelope logic to shape the I and Q output waveforms when ramping up or down at the beginning or end of a transmit burst. Besides providing all the necessary logic to perform /4 DQPSK modulation, the part also provides reconstruction filters to smooth the DAC outputs, providing continuous time analog outputs. The AD7010 generates differential analog outputs for both the I and Q signals. As it is a necessity for all digital mobile systems to use the lowest possible power, the device has power down options. The AD7010 is housed in a space efficient 24-pin SSOP (Shrink Small Outline Package).
FUNCTIONAL BLOCK DIAGRAM
DGND VDD VAA AGND
POWER Tx DATA /4 DQPSK MODULATOR 10-BIT I-DAC RECONSTRUCTION FILTERS ITx ITx
CALIBRATION CIRCUITRY
Tx CLK
10-BIT Q-DAC
RECONSTRUCTION FILTERS
QTx QTx
READY
AD7010
BIN
2.46V REFERENCE
BOUT
MCLK
BYPASS
MODE1
MODE2
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD7010SPECIFICATIONS1
Parameter DIGITAL MODE TRANSMIT No. of Channels Output Signal Range Differential Output Range Signal Vector Magnitude2 Error Vector Magnitude2 Offset Vector Magnitude2 JDC Spurious Power2, 3 @ 25 kHz @ 50 kHz @ 75 kHz @ 100 kHz, 150 kHz, 200 kHz REFERENCE & CHANNEL SPECIFICATIONS Reference, VREF Reference Accuracy I and Q Gain Matching Power Down Option LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES V DD IDD Transmit Section Active Transmit Section Powered Down4
(VAA = VDD = +5 V 10%; Test = AGND = DGND = 0 V; fMCLK = 2.688 MHz; Power = VDD. All specifications are TMIN to TMAX unless otherwise noted.)
AD7010ARS 2 VREF ± VREF/4 ± V REF/ 2 0.875 ± 7.5% 1 2.5 0.5 2.5 30 25 60 55 70 65 70 65 2.46 ±5 ± 0.2 Yes VDD0.9 0.9 10 10 VDD0.4 0.4 4.5/5.5 8 6 35 5 Units Test Conditions/Comments (ITxITx) and (QTxQTx) For Each Analog Output I Channel = (ITxITx) and Q Channel = (QTxQTx) Measured Differentially
Volts Volts Volts max % rms typ % rms max % typ % max dB typ dB max dB typ dB max dB typ dB max dB typ dB max Volts % dB max
Measured @ 10 kHz Power = 0 V
V min V max µA max pF max V min V max V min/V max mA max mA typ µA max µA max Power = VDD MCLK Active MCLK Inactive |IOUT| 40 µA |IOUT| 1.6 mA
NOTES 1 Operating temperature ranges as follows: A Version: 40°C to +85°C. 2 See Terminology. 3 Measured in continuous transmission and Burst transmission with the I and Q channels ramping up and down at the beginning and end of each burst. 4 Measured while the digital inputs to the transmit interface are static and equal to 0 V or V DD. Specifications subject to change without notice.
ORDERING GUIDE
Model AD7010ARS
Temperature Range 40°C to +85°C
Package Description
Package Option
Shrink Small Outline Package RS-24
2
REV. B
AD7010
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
ITx/QTx 20pF 20k
VDD Tx, VDD Rx to AGND . . . . . . . . . . . . . . . 0.3 V to +7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . 0.3 V to +0.3 V Digital I/O Voltage to DGND . . . . . 0.3 V to VDD to + 0.3 V Analog I/O Voltage to AGND . . . . . . . 0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . 40°C to +85°C Storage Temperature Range . . . . . . . . . . . . 65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C SSOP JA Thermal Impedance . . . . . . . . . . . . . . . . +122°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
AD7010
20k 40k ITx / QTx 20pF
Figure 1. Analog Output Load Test Circuit
Q MODULAR OUTPUT DURING FTEST
I
Table I.
MODE 1 0 0 1
MODE 2 0 1 X
Operation Digital JDC Mode FTEST Factory Test, Reserved
Figure 2. Modulator State During FTEST
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7010 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
MASTER CLOCK TIMING
Parameter t1 t2 t3 300 100 100
(VAA = VDD = +5 V otherwise noted.)
10%; AGND = DGND = O V. All specifications are TMIN to TMAX unless
Units ns min ns min ns min Description MCLK Cycle Time MCLK High Time MCLK Low Time
Limit at TA = 40 C to +85 C
t1 t2
MCLK CL 100pF TO OUTPUT PIN
1.6mA
IOL
+2.1V
t3
200µA
IOH
Figure 3. Master Clock (MCLK) Timing
Figure 4. Load Circuit for Digital Outputs
REV. B
3
AD7010 (V TRANSMIT SECTION TIMING T
Parameter t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 10 t1 10 4097t1 + 70 10 t1 10 t1 + 70 3t1 + 70 64t1 32t1 32t1 50 0 3 t1 124t1 7.5t9 30t1 10 10
AA
MIN
= VDD = +5 V 10%; AGND = DGND = 0 V, fMCLK = 2.688 MHz. All specifications are to TMAX unless otherwise noted.)
Units ns min ns max ns max ns min ns max ns max ns ns ns ns ns min ns min ns max ns max ns ns max ns max ns max Description POWER Setup Time. MCLK rising edge, after POWER high, to READY rising edge. BIN Setup Time. MCLK to READY low propagation delay. MCLK rising edge, after BIN high, to first TxCLK rising edge. TxCLK Cycle Time. TxCLK High Time. TxCLK Low Time. TxCLK falling edge to TxDATA setup time. TxCLK falling edge to TxDATA hold time. BIN low setup to last transmitted symbol after ramp down. BIN low hold to last transmitted symbol after ramp down. Ramp down cycle time after the last transmitted symbol. Last TxCLK falling edge to READY rising edge. Digital Output Rise Time. Digital Output Fall Time.
Limit at TA = 40°C to +85°C
MCLK
POWER
t4
READY
t7
t5
BIN
t6 t8 t9 t11 t12 t13
Xk
TxCLK
t10
Yk
TxDATA
Figure 5. Transmit Timing at the Start of a Tx Burst
MCLK
POWER
t17
READY BIN
t14 t15
TxCLK
t16
TxDATA XN+4 YN+4 XN+5 XN+8 YN+8
Figure 6. Transmit Timing at the End of a Tx Burst
4
REV. B
AD7010
PIN FUNCTION DESCRIPTION
SSOP Pin Number
Mnemonic
Function Positive power supply for analog section. Positive power supply for digital section, both supplies should be externally tied together. Analog ground for transmit section. Digital ground for transmit section, both grounds should be externally tied together.
POWER SUPPLY 19 V AA 5 V DD 14, 18, 23 AGND 6 DGND
ANALOG SIGNAL AND REFERENCE 13 BYPASS Reference decoupling output. A decoupling capacitor should be connected between this pin a and AGND. 16, 17 ITx, ITx Differential analog outputs for the I channel, representing true and complementary outputs of the I waveform. 21, 20 QTx, QTx Differential analog outputs for the Q channel, representing true and complementary outputs of the Q waveform. TRANSMIT INTERFACE AND CONTROL 7 MCLK Master clock, digital input. This pin should be driven by a 2.688 MHz CMOS compatible clock source in digital mode. 3 TxCLK This is a digital output, transmit clock. This may be used to clock in transmit data at 42 kHz. 4 TxDATA This is a digital input. This pin is used to clock in transmit data on the falling edge of TxCLK at a rate of 42 kHz. 2 BIN This is a digital input. This input is used to initiate the ramping up (BIN high) or down (BIN low) of the I and Q waveforms. 24 BOUT Burst out, digital output. This is the BIN input delayed by the pipeline delay, both digital and analog, of the AD7010. This can be used to turn on and off the RF amplifiers in synchronization with the I and Q waveforms. 1 POWER Transmit sleep mode, digital input. When this goes low, the AD7010 goes into sleep mode, drawing minimal current. When this pin goes high, the AD7010 is brought out of sleep mode and initiates a self-calibration routine to eliminate the offset between ITx & ITx and the offset between QTx & QTx. 12 READY Transmit ready, digital output. This output goes high once the self-calibration routine is complete. 9, 11 MODE1, Mode control, digital inputs. These are used to enter the AD7010 into three different MODE2 operating modes, see Table I. 8, 10, 15, 22 NC No Connects. These pins are no connects and should not be used as routes for other circuit signals.
SSOP PIN CONFIGURATION
POWER BIN TxCLK TxDATA VDD DGND MCLK NC MODE1 NC MODE2 READY
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20
BOUT AGND NC QTx QTx VAA AGND ITx ITx NC AGND BYPASS
AD7010
TOP VIEW (Not to Scale)
19 18 17 16 15 14 13
REV. B
5
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