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Details, datasheet, quote on part number:AD7011ARS
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Datasheet text preview:
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FEATURES Single +5 V Supply On-Chip /4 DQPSK Modulator Modulator Bypass Analog Mode Root-Raised Cosine Tx Filters, = 0.35 Two 10-Bit D/A Converters 4th Order Reconstruction Filters Differential Analog Outputs On-Chip Ramp Up/Down Power Control On-Chip Tx Offset Calibration Dual Mode Operation, Analog and Digital Very Low Power Dissipation, 30 mW typical Power Down Mode < 10 A On-Chip Voltage Reference 24-Pin SSOP APPLICATIONS American Digital Cellular Telephony American Analog Cellular Telephony
CMOS, ADC /4 DQPSK Baseband Transmit Port AD7011
GENERAL DESCRIPTION
The AD7011 is a complete low power, CMOS, /4 DQPSK modulator with single +5 V power supply. The part is designed to perform the baseband conversion of I and Q transmit waveforms in accordance with the American Digital Cellular Telephone system (TIA IS-54). The on-chip /4 Differential Quadrature Phase Shift Keying (DQPSK) digital modulator, which includes the root raised cosine filters, generates I and Q data in response to the transmit data stream. The AD7011 also contains ramp control envelope logic to shape the I and Q output waveforms when ramping up or down at the beginning or end of a transmit burst. Besides providing all the necessary logic to perform /4 DQPSK modulation, the part also provides reconstruction filters to smooth the DAC outputs, providing continuous time analog outputs. The AD7011 generates differential analog outputs for both the I and Q signals. As it is a necessity for all digital mobile systems to use the lowest possible power, the device has transmit and receive power-down options. The AD7011 is housed in a space efficient 24-pin SSOP (Shrink Small Outline Package).
FUNCTIONAL BLOCK DIAGRAM
DGND MCLK I BIN (Q DATA) ANALOG MODE SERIAL Q INTERFACE MODULATOR BYPASS I Tx DATA (I DATA) Tx CLK (FRAME) /4 DQPSK DIGITAL MODULATOR 10-BIT Q-DAC 10-BIT I-DAC RECONSTRUCTION FILTERS ITx ITx VDD VAA AGND
CALIBRATION CIRCUITRY
Q
RECONSTRUCTION FILTERS
QTx QTx
READY
AD7011
POWER
2.46V REFERENCE
BOUT
BYPASS
MODE1
MODE2
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
10%; Test = AGND = DGND = 0 V; Digital Mode, AA = VDD = +5 V fMCLK = 3.1104 MHz; Analog Mode, fMCLK = 2.56 MHz, POWER = VDD. All specifications are TMIN to TMAX unless otherwise noted.)
Parameter DIGITAL MODE TRANSMIT SPECIFICATIONS Number of Channels Output Signal Range Differential Output Range Signal Vector Magnitude2 Error Vector Magnitude2 Offset Vector Magnitude2 IS-54 Spurious Power2, 3 @ 30 kHz @ 60 kHz @ 90 kHz, 120 kHz ANALOG MODE SPECIFICATIONS No. of Channels Resolution Output Signal Range Differential Output Range DAC Update Rate SNR Differential Offset Error Group Delay Matching Between I & Q Outputs Coding Maximum and Minimum DAC Codes4 REFERENCE & CHANNEL SPECIFICATIONS Reference, VREF Reference Accuracy I and Q Gain Matching Power-Down Option LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH Output High Voltage VOL Output Low Voltage POWER SUPPLIES V DD IDD Transmit Section Active Transmit Section Powered Down5 AD7011ARS 2 V REF + V REF / 4 +V REF/ 2 0.875 ± 7.5% 1 2.5 0.5 2.5 35 30 70 65 75 70 2 10 VREF ± VREF/3 ± 2 VREF/3 160 60 55 ± 15 30 Twos Complement +450/450 2.46 ±5 ± 0.2 Yes VDD 0.9 0.9 10 10 VDD 0.4 0.4 4.5/5.5 8 6 35 5 Units Test Conditions/Comments (ITx ITx) and (QTx QTx) For Each Analog Output I Channel = (ITx ITx) and Q Channel = (QTx QTx) Measured Differentially
AD7011SPECIFICATIONS1 (V
Volts Volts Volts max % rms typ % rms max % typ % max dB typ dB max dB typ dB max dB typ dB max
(ITx ITx) and (QTx QTx) Bits Volts Volts kHz dB typ dB min mV max ns typ max/min Volts % dB max For Each Analog Output I Channel = (ITx ITx) and Q Channel = (QTx QTx) MCLK/16; fMCLK = 2.56 MHz Generating a 10 kHz Sine Wave Post Calibration
Measured @ 10 kHz Power = 0 V
V min V max FA max pF max V min V max V min/V max mA max mA typ µA max µA max P O W E R = VD D MCLK Active MCLK Inactive |IOUT| 40 µA |IOUT| 1.6 mA
NOTES 1 Operating temperature ranges as follows: A Version: 40°C to +85°C. 2 See terminology. 3 Measured in continuous transmission and Burst Mode with the I and Q channels ramping up and down at the beginning and end of a burst. 4 Headroom must be allowed for the transmit DACs such that offsets in I & Q transmit channels can be calibrated out. Therefore, the full range of the I and Q DACs are not available to the user. The user should ensure that binary codes greater than or less than the maximum or minimum are not loaded into the I or Q DACs. 5 Measured while the digital inputs to the transmit interface are static and equal to 0 V or V DD. Specifications subject to change without notice.
2
REV. B
AD7011
ITx/QTx 20pF 20k
AD7011
20k 40k ITx / QTx 20pF
Figure 1. Analog Output Test Load Circuit
MASTER CLOCK TIMING otherwise noted.)
Parameter t1 t2 t3 300 100 100
(VAA = VDD = +5 V
10%; AGND = DGND = 0 V. All specifications are TMIN to TMAX unless
Limit at TA = 40 C to +85 C
Units ns min ns min ns min
Description MCLK Cycle Time MCLK High Time MCLK Low Time
1.6mA
IOL
t1 t2
MCLK
TO OUTPUT PIN +2.1V CL 100pF 200µA IOH
t3
Figure 2. Master Clock (MCLK) Timing
Figure 3. Load Circuit for Digital Outputs
REV. B
3
AD7011 TRANSMIT SECTION TIMING
Parameter t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 10 t1 10 4097t1 + 70 10 t1 10 t1 + 70 3t1 + 70 64t1 32t1 32t1 50 0 3 t1 1 2 4 t1 7.5t9 30t1 10 10
(VAA = VDD = +5 V 10%; AGND = DGND = 0 V, fMCLK = 3.1104 MHz. All specifications are TMIN to TMAX unless otherwise noted.)
Units ns min ns max ns max ns min ns max ns max ns ns ns ns ns min ns min ns max ns max ns ns max ns max ns max Description Power Setup Time. MCLK rising edge, after Power high, to READY rising edge. BIN Setup Time. MCLK to READY propagation delay. MCLK rising edge, after BIN high, to first TxCLK rising edge. TxCLK Cycle Time. TxCLK High Time. TxCLK Low Time. TxCLK falling edge to TxDATA setup time. TxCLK falling edge to TxDATA hold time. BIN low setup to Last transmitted symbol after ramp down. BIN low hold to Last transmitted symbol after ramp down. Ramp Down cycle time after the last transmitted symbol. Last TxCLK falling edge to READY rising edge. Digital Output Rise Time. Digital Output Fall Time.
Limit at TA = 40 C to +85 C
MCLK
POWER
t4
READY
t7
t5
BIN
t6 t8 t9 t11 t12 t13 t10
X Y
TxCLK
TxDATA
k
k
Figure 4. Transmit Timing at the Start of a Tx Burst
MCLK
POWER
t17
READY BIN
t14 t15
TxCLK
t16
TxDATA X
N+4
Y
N+4
X
N+5
X
N+8
Y
N+8
Figure 5. Transmit Timing at the End of a Tx Burst
4
REV. B
AD7011 ANALOG MODE TIMING
Parameter t20 t21 t22 t23 t24 15 15 15t1 16t1 15 15
(VAA = VDD = +5 V otherwise noted.)
10%. AGND = DGND = 0 V. All specifications are TMIN to TMAX unless
Units ns min ns min ns max ns ns min ns min Description MCLK Rising Edge to FRAME Setup Time. MCLK Rising Edge to FRAME Hold Time. FRAME Cycle Time. MCLK Rising Edge to Data Setup Time. MCLK Rising Edge to Data Hold Time.
Limit at TA = 40°C to +85°C
MCLK
t20
FRAME
t22
21
t23 t24
I DATA DB9 DB8 DB1 DB0 DB9
Q DATA
DB9
DB8
DB1
DB0
DB9
Figure 6. Analog Mode Serial Interface Timing
Q MODULAR OUTPUT DURING FTEST
t
DB8
DB7
DB8
DB7
I
Table I.
MODE 1 0 1 0 1
MODE 2 0 0 1 1
Operation Digital TIA Mode Analog Mode FTEST Factory Test, Reserved
Figure 7. Modulator State During FTEST
Table II.
Mode of Operation Digital Mode Analog Mode
MODE 1 0 1
MODE 2 0 0
MCLK 3.1104 MHz 2.56 MHz
Digital Bit Rate 48.6 kHz N/A
DAC Update Rate N/A 160 kHz
REV. B
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