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Details, datasheet, quote on part number:AD7013ARS
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FEATURES Single +5 V Supply Receive Channel Differential or Single-Ended Analog Inputs Auxiliary Set of Analog I & Q Inputs Two Sigma-Delta A/D Converters Choice of Two Digital FIR Filters Root-Raised-Cosine Rx Filters, = 0.35 Brick Wall FIR Rx Filters On-Chip or User Rx Offset Calibration ADC Sampling Vernier Three Auxiliary DACs On-Chip Voltage Reference Low Active Power Dissipation, Typical 45 mW Low Sleep Mode Power Dissipation, <50 µW 28-Pin SSOP APPLICATIONS American TIA Digital Cellular Telephony American Analog Cellular Telephony Digital Baseband Receivers GENERAL DESCRIPTION The AD7013 is a complete low power, CMOS, TIA IS-54 baseband receive port with single +5 V power supply. The part is
CMOS TIA IS-54 Baseband Receive Port AD7013
designed to perform the baseband conversion of I and Q waveforms in accordance with the American (TIA IS-54) Digital Cellular Telephone system. The receive path consists of two high performance sigma-delta ADCs, each followed by a FIR digital filter. A primary and auxiliary set of IQ differential analog inputs are provided, where either can be selected as inputs to the sigma-delta ADCs. Also, a choice of two frequency responses are available for the receive FIR filters; a Root-Raised-Cosine filter for digital mode or a brick wall response for analog mode. Differential analog inputs are provided for both I and Q channels. On-chip calibration logic is also provided to remove either on-chip offsets or remove system offsets. A 16-bit serial interface is provided, interfacing easily to most DSPs. The receive path also provides a means to vary the sampling instant, giving a resolution to 1/32 of a symbol interval. The auxiliary section provides two 8-bit DACs and one 10-bit DAC for functions such as automatic gain control (AGC), automatic frequency control (AFC) and power amplifier control. As it is a necessity for all digital mobile systems to use the lowest possible power, the device has receive and auxiliary power down options. The AD7013 is housed in a space efficient 28-pin SSOP (Shrink Small Outline Package).
FUNCTIONAL BLOCK DIAGRAM
MCLK DGND VDD AUX DAC1 AUX DAC2 AUX DAC3 FS ADJUST VAA AGND
DxCLK DATA IN FRAME IN MODE1 FRAME OUT SERIAL INTERFACE
10-BIT AUX DAC
8-BIT AUX DAC
8-BIT AUX DAC
FULL-SCALE ADJUST AGND AGND
LATCH
LATCH
LATCH
AD7013
1.23V REFERENCE ANALOG MODE FIR DIGITAL FILTER ROOT RAISED COSINE FIR DIGITAL FILTER BYPASS IRx MODULATOR SWITCHED CAP FILTER IRx MUX AUX IRx AUX IRx QRx OFFSET ADJUST ANALOG MODE FIR DIGITAL FILTER ROOT RAISED COSINE FIR DIGITAL FILTER MODULATOR SWITCHED CAP FILTER QRx MUX AUX QRx AUX QRx
Rx CLK RECEIVE CHANNEL SERIAL INTERFACE
OFFSET ADJUST
Rx DATA Rx FRAME
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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AD7013SPECIFICATIONS
Parameter RECEIVE SECTION ADC SPECIFICATION Number of Input Channels 4
1
(VAA = VDD = +5 V ± 10%; AGND = DGND = 0 V; fMCLK = 6.2208 MHz; TA = TMIN to TMAX, unless otherwise noted)
Units Test Conditions/Comments
AD7013A
(IRxIRx) and QRxQRx); CR12 = 0 (AUX IRxAUX IRx) and (AUX QRxAUX QRx); CR12 = 1 Bits Volts p-p Volts Volts Volts min/max Volts min/max % mV mV
Number of ADC Channels Resolution ADC Signal Range Differential Signal Range Single-Ended Signal Range VB I A S Input Range Accuracy Accuracy Bias Offset Error
2 15 2.6 VBIAS ± 0.65 VBIAS ± 1.3 0.65 to (VAA0.65) 1.3 to (VAA1.3) ± 7.5 ± 7.5 ± 55
Measured Using an Input Sine Wave of 3 kHz For Both Noninverting and Inverting Analog Inputs For Noninverting Analog Inputs; Inverting Analog Inputs = VBIAS Differential Single-Ended
Autocalibration; VBIAS = min/max User Calibration; I & Q Offset Adjust Registers Equal to Zero Measured Using an Input Sine Wave of 3 kHz with Both Noninverting and Inverting Inputs Tied Together Digital Mode Filter; CR11 = 0 Analog Mode Filter; CR11 = 1 Digital Mode Filter; CR11 = 0 Analog Mode Filter; CR11 = 1 MCLK = 6.2208 MHz/5.12 MHz; MCLK/4 MCLK = 6.2208 MHz/5.12 MHz; 4 × Sampling of the Symbol Rate, MCLK/64 MCLK = 6.2208 MHz/5.12 MHz; 2 × Sampling of the Symbol Rate, MCLK/128 MCLK = 6.2208 MHz
Dynamic Specifications CMRR
40
dB typ
Dynamic Range SNR 2
Input Sampling Rate Output Word Rate
70 65 65 68 60 63 1.5552/1.28 97.2/80 48.6/40
dB typ dB typ dB min dB typ dB min dB typ MHz kHz kHz
RECEIVE DIGITAL FILTERS Digital Mode Root-Raised-Cosine Settling Time Absolute Group Delay Frequency Response 07.8975 kHz 11.9 kHz 16.4025 kHz > 30 kHz Analog Mode Brick Wall Filter Settling Time Absolute Group Delay Frequency Response 08 kHz 11.4 kHz 15 kHz >17 kHz
= 0.35 329.2 164.6 ± 0.05 3.0 19 66
µs µs dB max dB dB dB max MCLK = 5.12 MHz
400 200 0 to 0.5 3.0 24 68
µs µs dB max dB dB dB max
TIA IS-54 RECEIVE SPECIFICATIONS Error Vector Magnitude 3 Error Offset Magnitude3
2 1
% rms typ % rms typ
Measured Using a Full-Scale Input
2
REV. A
AD7013
Parameter AUXILIARY SECTION Resolution DC Accuracy Integral Differential Zero Code Leakage Gain Error Output Full-Scale Current Output Impedance4 Output Voltage Compliance Coding Power Down Option REFERENCE SPECIFICATIONS VR E F Reference Accuracy Reference Impedance LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES VD D I DD 5 All Sections Active AUX DAC1 AUX DAC2 AUX DAC3 10 8 8 ±3 1.5/+4 ± 500 ± 7.5 566 ±1 ±1 ± 500 ± 7.5 280 2 2.6 Binary Yes 1.23 ±5 20 ±1 ±1 ± 500 ± 7.5 280 Bits LSBs max LSBs max nA max % max µA M typ Volts max AD7013A Units Test Conditions/Comments
AUX DAC2 & AUX DAC3 Guaranteed Monotonic
RSET = 18 k
Volts typ % max k typ V min V max µA max pF max |IOUT| 40 µA |IOUT| 1.6 mA
V DD 0 . 9 0.9 10 10
V DD 0 . 4 0.4
V min V max
4.5/5.5 10.5 9 8.6
V M I N/ V M A X mA max mA typ mA max CR14 = CR15 = CR16 = CR17 = 1 MCLK = 6.2208 MHz; 80 pF Load on DxCLK CR14 = 1; CR15 = CR16 = CR17 = 0 MCLK = 6.2208 MHz; 80 pF Load on DxCLK CR14 = 0; CR15 = CR16 = CR17 = 1; MCLK Inactive, MCLK = 0 V CR14 = CR15 = CR16 = 0; CR17 = 1; MCLK Inactive, MCLK = 0 V CR14 = CR15 = CR16 = CR17 = 0 MCLK = 6.2208 MHz; 80 pF Load on DxCLK MCLK =100 kHz; 80 pF Load on DxCLK MCLK Inactive, MCLK = 0 V
ADCs Active Only
AUX DACs Active Only 10-Bit AUX DAC Active All Sections Powered Down6
2.2 1.6 2
mA max mA max mA max
30 10
µA typ µA max
NOTES 1 Operating temperature ranges as follows: A version: 40°C to +85°C. 2 SNR calculation includes noise and distortion components. 3 See Terminology. 4 Sampled tested only. 5 Measured while the digital inputs are static and equal to 0 V or V DD. 6 With all sections powered down, I DD is proportional to the capacitive load on DxCLK. For example, I DD is typically 1.7 mA with 80 pF load and 600 µA with 10 pF load. Specifications subject to change without notice.
REV. A
3
AD7013
TERMINOLOGY Sampling Rate This is the rate at which the modulators on the receive channels sample the analog input. Output Rate This is the rate at which data words are made available at the RxDATA pin. Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the DAC or ADC transfer function. Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the DAC or ADC. Dynamic Range Dynamic Range is the ratio of the maximum rms input signal to the rms noise of the converter, expressed logarithmically, in decibels (dB = 20 log10 [ratio]). Signal to (Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the output of the receive channel. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f S/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for a sine wave is given by: Signal to (Noise + Distortion) = (6.02N + 1.76) dB Settling Time This is the digital filter settling time in the AD7013 receive section. Bias Offset Error This is the amount of offset in the receive channel ADC when the differential inputs are tied together. Receive Error Vector Magnitude This is a measure of the rms signal error vector introduced by the receive Root-Raised Cosine digital filter. This is measured by applying an ideal transmit signal (i.e., an ideal /4 DQPSK modulator and an ideal transmit Root-Raised Cosine filter) to the receive channel and measuring the resulting rms error vector. Offset Vector Magnitude This is a measure of the offset vector introduced by the AD7013 as illustrated in the figure below. The offset vector is calculated so as to minimize the rms error vector for each of the constellation points.
Q ERROR VECTOR
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25°C unless otherwise noted)
VAA, VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +0.3 V Digital I/O Voltage to DGND . . . . . . . . . . . 0.3 V to VDD +0.3 V Analog I/O Voltage to AGND . . . . . . . . . . . 0.3 V to VDD +0.3 V Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . . . . 40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . . . 65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . +150°C SSOP JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . +122°C/W Lead Temperature Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions extended periods may affect device reliability.
PIN CONFIGURATION
VAA IRx AUX IRx IRx AUX IRx QRx AUX QRx QRx AUX QRx AGND MODE1 Rx FRAME Rx DATA Rx CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 BYPASS 27 AGND 26 FS ADJUST 25 AGND 24 AUX DAC1 23 AUX DAC2 22 AUX DAC3 TOP VIEW (Not to Scale) 21 VDD 20 MCLK 19 DxCLK 18 DATA IN 17 FRAME IN 16 DGND 15 FRAME OUT
AD7013
ORDERING GUIDE Model AD7013ARS
*RS = SSOP.
Temperature Range 40°C to +85°C
Package Option* RS-28
SIGNAL VECTOR OFFSET VECTOR
I
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this device features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
4
REV. A
AD7013
PIN FUNCTION DESCRIPTIONS SSOP Pin Number Mnemonic Function Positive Power Supply for Analog section. A 0.1 µF decoupling capacitor should be connected between this pin and AGND. Positive Power Supply for Digital section. A 0.1 µF decoupling capacitor should be connected between this pin and DGND. Both V AA and VDD should be externally tied together. Analog Ground. Digital Ground. Both AGND and DGND should be externally tied together. Reference Decoupling Output. A 10 nF decoupling capacitor should be connected between this pin and AGND. Differential Analog Inputs for the I receive channel. These are the primary receive analog inputs and are selected by setting CR12 to a zero in the command register. Differential Analog Inputs for the Q receive channel. These are the primary receive analog inputs and are selected by setting CR12 to a zero in the command register. Auxiliary Differential Analog Inputs for the I receive channel. The Auxiliary inputs are selected by setting CR12 to a one in the command register. Auxiliary Differential Analog Inputs for the Q receive channel. The Auxiliary inputs are selected by setting CR12 to a one in the command register. Analog output from the 10-bit auxiliary DAC. Analog outputs from the 8-bit auxiliary DACs. An external resistor is connected from this pin to ground to determine the fullscale current for AUX DAC1, AUX DAC2, and AUX DAC3. Master Clock, Digital Input. When operating in IS-54 Digital mode this pin should be driven by a 6.2208 MHz CMOS compatible clock source and 5.12 MHz clock source for Analog Mode. Transmit Clock, Digital Output. This is a continuous clock equal to MCLK/2 which can be used to clock the serial port of a DSP. Digital Input. This is used to frame the clocking in of 16-bit words for the control registers serial interface. Digital Input. Transmit Serial Data, digital input. This pin is used to clock in data for the serial interface on the rising edge of DxCLK. Digital Output. This output represents a buffered version of FRAME IN and is controlled by the MODE1 pin. This pin can be used to daisy chain the FRAME IN signal. Digital Input. This pin determines the state of FRAME OUT. When MODE1 is high, FRAME IN is buffered and made available on FRAME OUT. When MODE1 is low, FRAME OUT is in 3-STATE. Output Clock for the receive section interface. Synchronization output for framing I and Q data at the receive interface. Receive Data, digital output. I and Q data are available at this pin via a 16-bit serial interface. Data is valid on the falling edge of RxCLK. I and Q data are clocked out as two 16-bits words, with the I word being clocked first. The last bit in each 16-bit word is a I/Q flag bit, indicating whether that word is an I word or a Q word.
POWER SUPPLY 1 V AA 21 V DD
10, 25, 27 16
AGND DGND
ANALOG SIGNAL AND REFERENCE 28 BYPASS 2, 4 6, 8 3, 5 7, 9 24 3, 22 26 IRx, IRx QRx, QRx AUX IRx, AUX IRx AUX QRx, AUX QRx AUX DAC1 AUX DAC2, AUX DAC3 FS ADJUST
SERIAL INTERFACE AND CONTROL 20 MCLK
19 17 18 15
DxCLK FRAME IN DATA IN FRAME OUT
11
MODE1
RECEIVE INTERFACE AND CONTROL 14 RxCLK 12 RxFRAME 13 RxDATA
REV. A
5
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