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Details, datasheet, quote on part number:AD7248ABR
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Datasheet text preview:
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FEATURES 12-Bit CMOS DAC with Output Amplifier and Reference Improved AD7245/AD7248: 12 V to 15 V Operation 1/2 LSB Linearity Grade Faster Interface30 ns typ Data Setup Time Extended Plastic Temperature Range (40 C to +85 C) Single or Dual Supply Operation Low Power65 mW typ in Single Supply Parallel Loading Structure: AD7245A (8+4) Loading Structure: AD7248A
LC2MOS 12-Bit DACPORTs AD7245A/AD7248A
AD7245A FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD7245A/AD7248A is an enhanced version of the industry standard AD7245/AD7248. Improvements include operation from 12 V to 15 V supplies, a ± 1/2 LSB linearity grade, faster interface times and better full scale and reference variations with VDD. Additional features include extended temperature range operation for commercial and industrial grades. The AD7245A/AD7248A is a complete, 12-bit, voltage output, digital-to-analog converter with output amplifier and Zener voltage reference on a monolithic CMOS chip. No external user trims are required to achieve full specified performance. Both parts are microprocessor compatible, with high speed data latches and double-buffered interface logic. The AD7245A accepts 12-bit parallel data which is loaded into the input latch on the rising edge of CS or WR. The AD7248A has an 8-bit wide data bus with data loaded to the input latch in two write operations. For both parts, an asynchronous LDAC signal transfers data from the input latch to the DAC latch and updates the analog output. The AD7245A also has a CLR signal on the DAC latch which allows features such as power-on reset to be implemented. The on-chip 5 V buried Zener diode provides a low noise, temperature compensated reference for the DAC. For single supply operation, two output ranges of 0 V to +5 V and 0 V to +10 V are available, while these two ranges plus an additional ± 5 V range are available with dual supplies. The output amplifiers are capable of developing +10 V across a 2 k load to GND. The AD7245A/AD7248A is fabricated in linear compatible CMOS (LC2MOS), an advanced, mixed technology process that combines precision bipolar circuits with low power CMOS logic. The AD7245A is available in a small, 0.3" wide, 24-pin DIP and
AD7248A FUNCTIONAL BLOCK DIAGRAM
SOIC and in 28-terminal surface mount packages. The AD7248A is packaged in a small, 0.3" wide, 20-pin DIP and SOIC and in 20-terminal surface mount packages.
PRODUCT HIGHLIGHTS
1. The AD7245A/AD7248A is a 12-bit DACPORT® on a single chip. This single chip design and small package size offer considerable space saving and increased reliability over multichip designs. 2. The improved interface times on the part allows easy, direct interfacing to most modern microprocessors. 3. The AD7245A/AD7248A features a wide power supply range allowing operation from 12 V supplies.
DACPORT is a registered trademark of Analog Devices, Inc.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD7245A/AD7248ASPECIFICATIONS (V = +12 V to +15 V, V AGND = DGND = O V, R = 2 k , C = 1OO pF. All specifications T to T unless otherwise noted.)
DD 1 L L MIN MAX
SS
= O V or 12 V to 15 V,1
Parameter STATIC PERFORMANCE Resolution Relative Accuracy @ +25°C3 TMIN to TMAX TMIN to TMAX Differential Nonlinearity3 Unipolar Offset Error @ +25°C3 TMIN to TMAX Bipolar Zero Error @ +25°C3 TMIN to TMAX DAC Gain Error3, 6 Full-Scale Output Voltage Error 7 @ +25°C Full Scale/VDD Full Scale/VSS Full-Scale Temperature Coefficient8 REFERENCE OUTPUT REF OUT @ +25°C REF OUT/VDD Reference Temperature Coefficient Reference Load Change (REF OUT vs. I) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance9 ANALOG OUTPUTS Output Range Resistors Output Voltage Ranges10 Output Voltage Ranges10 DC Output Impedance AC CHARACTERISTICS9 Voltage Output Settling Time Positive Full-Scale Change Negative Full-Scale Change Output Voltage Slew Rate Digital Feedthrough3 Digital-to-Analog Glitch Impulse POWER REQUIREMENTS V DD V SS IDD @ +25°C TMlN to TMAX ISS (Dual Supplies)
A2 Version 12 ± 3/4 ±1 ±1 ±3 ±5 ±3 ±5 ±2 ± 0.2 ± 0.06 ± 0.01 ± 30
B2 Version 12 ± 1/2 ± 3/4 ± 1/2 ±1 ±3 ±5 ±2 ±4 ±2 ± 0.2 ± 0.06 ± 0.01 ± 30
T2 Version 12 ± 1/2 ± 3/4 ±1 ±3 ±5 ±2 ±4 ±2 ± 0.2 ± 0.06 ± 0.01 ± 40
Units Bits LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max % of FSR max % of FSR/V max % of FSR/V max ppm of FSR/°C max
Test Conditions/Comments
VDD = 15 V ± 5% Guaranteed Monotonic VSS = 0 V or 12 V to 15 V4 Typical Tempco is ± 3 ppm of FSR5/°C. ROFS connected to REF OUT; VSS = 12 V to 15 V4 Typical Tempco is ± 3 ppm of FSR5/°C. VDD = +15 V VDD = +12 V to +15 V4 VSS = 12 V to 15 V4 VDD = +15 V VDD = +15 V VDD = +12 V to +15 V4 Referenee Load Current Change (0100 µA)
4.99/5.01 4.99/5.01 2 2 ± 25 ± 25 1 2.4 0.8 ± 10 8 15/30 +5, +10 +5, +10, ±5 0.5 1 2.4 0.8 ± 10 8 15/30 +5, +10 +5, +10, ±5 0.5
4.99/5.01 V min/V max 2 mV/V max ± 35 ppm/°C typ 1 2.4 0.8 ± 10 8 15/30 +5, +10 +5, +10, ±5 0.5 mV max V min V max µA max pF max k min/k max V V typ
VIN = 0 V to VDD
VSS = 0 V; Pin Strappable VSS = 12 V to 15 V;4 Pin Strappable
7 7 2 10 30 +10.8/ +16.5 10.8/ 16.5 9 10 3
7 7 2 10 30 +11.4/ +15.75 11.4/ 15.75 9 10 3
10 10 1.5 10 30 +11.4/ +15.75 11.4/ 15.75 9 12 5
µs max µs max V/µs min nV-s typ nV-s typ V min/ V max V min/ V max mA max mA max mA max
Settling Time to Within ± 1/2 LSB of Final Value DAC Latch All 0s to All 1s DAC Latch All 1s to All 0s; VSS = 12 V to 15 V4
For Specified Performance Unless Otherwise Stated For Specified Performance Unless Otherwise Stated Output Unloaded; Typically 5 mA Output Unloaded Output Unloaded; Typically 2 mA
NOTES 1 Power supply tolerance is ± 10% for A Version and ± 5% for B and T Versions. 2 Temperature ranges are as follows: A/B Versions; 40°C to +85°C; T Version; 55°C to +125°C. 3 See Terminology. 4 With appropriate power supply tolerances. 5 FSR means Full-Scale Range and is 5 V for the 0 V to +5 V output range and 10 V for both the 0 V to +10 V and ± 5 V output ranges. 6 This error is calculated with respect to the reference voltage and is measured after the offset error has been allowed for. 7 This error is calculated with respect to an ideal 4.9988 V on rhe 0 V to +5 V and ± 5 V ranges; it is calculated with respect to an ideal 9.9976 V on the 0 V to +10 V range. It includes the effects of internal voltage reference, gain and offset errors. 8 Full-Scale TC = FS/T, where FS is the full-scale change from T A = +25°C to TMIN or TMAX. 9 Sample tested at +25°C to ensure compliance. 10 0 V to +10 V output range is available only when V DD +14.25 V. Specifications subject to change without notice.
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AD7245A/AD7248A SWITCHING CHARACTERISTICS1 (V
Parameter t1 @ +25°C TMIN to TMAX t2 @ +25°C TMIN to TMAX t3 @ +25°C TMIN to TMAX t4 @ +25°C TMIN to TMAX t5 @ +25°C TMIN to TMAX t6 @ +25°C TMIN to TMAX t7 @ +25°C TMIN to TMAX t8 (AD7245A only) @ +25°C TMIN to TMAX 40 80 40 80 40 100 40 100 ns typ ns min ns typ ns min Load DAC Pulse Width 10 10 10 10 ns min ns min Data Valid to Write Hold Time 40 80 40 80 ns typ ns min Data Valid to Write Setup Time 0 0 0 0 ns min ns min Chip Select to Write Hold Time 0 0 0 0 ns min ns min Chip Select to Write Setup Time 40 80 40 100 ns typ ns min Write Pulse Width 55 80 55 100 ns typ ns min Chip Select Pulse Width
DD
= +12 V to +15 V;2 VSS = O V or 12 V to 15 V;2 See Figures 5 and 7.)
T Version Units Conditions
A, B Versions
Clear Pulse Width
NOTES 1 Sample tested at +25°C to ensure compliance. 2 Power supply tolerance is ± 10% for A Version and ± 5% for B and T Versions.
ABSOLUTE MAXIMUM RATINGS 1
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . .0.3 V to +17 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . .0.3 V to +17 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.3 V to +34 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, VDD Digital Input Voltage to DGND . . . . . . . . 0.3 V, VDD +0.3 V VOUT to AGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD VOUT to VSS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +24 V VOUT to VDD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 V, 0 V REF OUT2 to AGND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature Commercial (A, B Versions) . . . . . . . . . . . 40°C to +85°C Extended (S Version) . . . . . . . . . . . . . . . 55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . 65°C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 The output may be shorted to voltages in this range provided the power dissipation of the package is not exceeded. V OUT short circuit current is typically 80 mA.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7245A/AD7248A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD7245A/AD7248A
AD7245A ORDERING GUIDE DAC GAIN ERROR
Modell AD7245AAN AD7245ABN AD7245AAQ AD7245ATQ3 AD7245AAP AD7245AAR AD7245ABR AD7245ATE3
Temperature Range 40°C to +85°C 40°C to +85°C 40°C to +85°C 55°C to +125°C 40°C to +85°C 40°C to +85°C 40°C to +85°C 55°C to +125°C
Relative Accuracy ± 3/4 LSB ± 1/2 LSB ± 3/4 LSB ± 3/4 LSB ± 3/4 LSB ± 3/4 LSB ± 1/2 LSB ± 3/4 LSB
Package Option2 N-24 N-24 Q-24 Q-24 P-28A R-24 R-24 E-28A
DAC Gain Error is a measure of the output error between an ideal DAC and the actual device output with all 1s loaded after offset error has been allowed for. It is, therefore defined as: Measured Value--Offset--Ideal Value where the ideal value is calculated relative to the actual reference value.
UNIPOLAR OFFSET ERROR
Unipolar Offset Error is a combination of the offset errors of the voltage mode DAC and the output amplifier and is measured when the part is configured for unipolar outputs. It is present for all codes and is measured with all 0s in the DAC register.
BIPOLAR ZERO OFFSET ERROR
NOTES 1 To order MIL-STD-883, Class B. processed parts, add /883B to part number. Contact our local sales office for military data sheet and availability. 2 E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC. 3 This grade will be available to /883B processing only.
Bipolar Zero Offset Error is measured when the part is configured for bipolar output and is a combination of errors from the DAC and output amplifier. It is present for all codes and is measured with a code of 2048 (decimal) in the DAC register.
SINGLE SUPPLY LINEARITY AND GAIN ERROR
AD7248A ORDERING GUIDE
Modell AD7248AAN AD7248ABN AD7248AAQ AD7248ATQ3 AD7248AAP AD7248AAR AD7248ABR
Temperature Range 40°C to +85°C 40°C to +85°C 40°C to +85°C 55°C to +125°C 40°C to +85°C 40°C to +85°C 40°C to +85°C
Relative Accuracy ± 3/4 LSB ± 1/2 LSB ± 3/4 LSB ± 3/4 LSB ± 3/4 LSB ± 3/4 LSB ± 1/2 LSB
Package Option2 N-20 N-20 Q-20 Q-20 P-20A R-20 R-20
NOTES 1 To order MIL-STD-883, Class B, processed parts, add /883B to part number. Contact our local sales office for military data sheet and availability. 2 N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC. 3 This grade will be available to /883B processing only.
TERMINOLOGY
RELATIVE ACCURACY
The output amplifier of the AD7245A/AD7248A can have a true negative offset even when the part is operated from a single positive power supply. However, because the lower supply rail to the part is 0 V, the output voltage cannot actually go negative. Instead the output voltage sits on the lower rail and this results in the transfer function shown. This is an offset effect and the transfer function would have followed the dotted line if the output voltage could have gone negative. Normally, linearity is measured after offset and full scale have been adjusted or allowed for. On the AD7245A/AD7248A the negative offset is allowed for by calculating the linearity from the code which the amplifier comes off the lower rail. This code is given by the negative offset specification. For example, the single supply linearity specification applies between Code 3 and Code 4095 for the 25°C specification and between Code 5 and Code 4095 over the TMIN to TMAX temperature range. Since gain error is also measured after offset has been allowed for, it is calculated between the same codes as the linearity error. Bipolar linearity and gain error are measured between Code 0 and Code 4095.
Relative Accuracy, or end-point nonlinearity, is a measure of the actual deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after allowing for zero and full scale and is normally expressed in LSBs or as a percentage of full-scale reading.
DIFFERENTIAL NONLINEARITY
OUTPUT VOLTAGE
Differential Nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ± 1 LSB max over the operating temperature range ensures monotonicity.
DIGITAL FEEDTHROUGH
0V NEGATIVE OFFSET
{
DAC CODE
Digital Feedthrough is the glitch impulse injected from the digital inputs to the analog output when the inputs change state. It is measured with LDAC high and is specified in nV-s.
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AD7245A/AD7248A
AD7248A PIN FUNCTION DESCRIPTION (DIP PIN NUMBERS)
Pin l 2
Mnemonic V SS R OFS
Description Negative Supply Voltage (0 V for single supply operation). Bipolar Offset Resistor. This provides access to the on-chip application resistors and allows different output voltage ranges. Reference Output. The on-chip reference is provided at this pin and is used when configuring the part for bipolar outputs. Analog Ground. Data Bit 11. Most Significant Bit (MSB). Data Bit 10 to Data Bit 5. Digital Ground. Data Bit 4 to Data Bit 1. Data Bit 0. Least Significant Bit (LSB). Chip Select Input (Active LOW). The device is selected when this input is active.
Pin 19
Mnemonic WR
Description Write Input (Active LOW). This is used in conjunction with CS to write data into the input latch of the AD7245A. Load DAC Input (Active LOW). This is an asynchronous input which when active transfers data from the input latch to the DAC latch. Clear Input (Active LOW). When this input is active the contents of the DAC latch are reset to all 0s. Positive Supply Voltage. Feedback Resistor. This allows access to the amplifier's feedback loop. Output Voltage. Three different output voltage ranges can be chosen: 0 V to +5 V, 0 V to +10 V or 5 V to +5 V.
20
LDAC
3
REF OUT
21
CLR
4 5 6-11 12
AGND DB11 DB10-DB5 DGND
22 23 24
V DD RFB V OUT
13-16 DB4-DB1 17 18 DB0 CS
AD7245A PIN CONFIGURATIONS DIP and SOIC LCCC
PLCC
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