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Details, datasheet, quote on part number:AD7376A-50
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Datasheet text preview:
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FEATURES 128 Position Potentiometer Replacement 10 k , 50 k , 100 k , 1 M Power Shutdown: Less than 1 A 3-Wire SPI Compatible Serial Data Input +5 V to +30 V Single Supply Operation 5 V to 15 V Dual Supply Operation Midscale Preset APPLICATIONS Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage-to-Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching Power Supply Adjustment GENERAL DESCRIPTION
SDO
15 V Operation Digital Potentiometer AD7376*
FUNCTIONAL BLOCK DIAGRAM
AD7376
Q 7-BIT SERIAL REGISTER SDI CLK CS D CK 7 7-BIT LATCH R 7
VDD A W B SHDN VSS
GND
RS
SHDN
The AD7376 provides a single channel, 128-position digitallycontrolled variable resistor (VR) device. This device performs the same electronic adjustment function as a potentiometer or variable resistor. These products were optimized for instrument and test equipment applications where a combination of high voltage with a choice between bandwidth or power dissipation are available as a result of the wide selection of end-to-end terminal resistance values. The AD7376 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the SPI-compatible serial-input register. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. The variable resistor offers a completely programmable value of resistance between the A terminal and the wiper or the B terminal and the wiper. The fixed A to B terminal resistance of 10 k, 50 k, 100 k or 1 M has a nominal temperature coefficient of 300 ppm/°C. The VR has its own VR latch which holds its programmed resistance value. The VR latch is updated from an internal serial-toparallel shift register which is loaded from a standard 3-wire serial-input digital interface. Seven data bits make up the data word clocked into the serial data input register (SDI). Only the last seven bits of the data word loaded are transferred into the 7-bit VR latch when the CS strobe is returned to logic high. A serial data output pin (SDO) at the opposite end of the serial register allows simple daisy-chaining in multiple VR applications without additional external decoding logic. The reset (RS) pin forces the wiper to the midscale position by loading 40H into the VR latch. The SHDN pin forces the resistor
*Patent Number: 5495245
to an end-to-end open circuit condition on the A terminal and shorts the wiper to the B terminal, achieving a microwatt power shutdown state. When shutdown is returned to logic high, the previous latch settings put the wiper in the same resistance setting prior to shutdown as long as power to VDD is not removed. The digital interface is still active in shutdown so that code changes can be made that will produce a new wiper position when the device is taken out of shutdown. The AD7376 is available in both surface mount (SOL-16) and the 14-lead plastic DIP package. For ultracompact solutions selected models are available in the thin TSSOP package. All parts are guaranteed to operate over the extended industrial temperature range of 40°C to +85°C. For operation at lower supply voltages (+3 V to +5 V), see the AD8400/AD8402/ AD8403 products.
SDI (DATA IN)
1 0
DX
DX
t DS t DH
SDO (DATA OUT)
1
D'X
0
D'X
t PD_MAX t CH
1
CLK
0
t CS1 t CL t CSS t CSH t CSW tS
t CSH0
1
CS
0
VOUT
VDD
0V
1 LSB ERROR BAND 1 LSB
Figure 1. Detail Timing Diagram
The last seven data bits clocked into the serial input register will be transferred to the VR 7-bit latch when CS returns to logic high. Extra data bits are ignored.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1997
AD7376SPECIFICATIONS
(VDD/VSS =
Parameter Symbol
ELECTRICAL CHARACTERISTICS unless otherwise noted.)
Conditions
15 V
10% or
5V
10%, VA = +VDD, VB = VSS/0 V, 40 C < TA < +85 C
Typ1 ± 0.25 ± 0.5 300 120 200 7 1 1 2 0 VS S
Min 1 1 30
Max +1 +1 30 200
Units LSB LSB % ppm/ °C Bits LSB LSB ppm/ °C LSB LSB V pF pF µA nA V V V V µA pF V V mA mA mA mW %/% %/% kHz kHz kHz % µs n V H z ns ns ns ns ns ns ns ns ns
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs) Resistor Differential NL2 R-DNL RWB, VA = NC Resistor Nonlinearity2 R-INL RWB, VA = NC Nominal Resistor Tolerance R TA = +25°C Resistance Temperature Coefficient R A B/ T VAB = VDD, Wiper = No Connect Wiper Resistance RW IW = ± 15 V/RNOMINAL Wiper Resistance RW IW = ± 5 V/RNOMINAL DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs) Resolution N Integral Nonlinearity3 INL Differential Nonlinearity3 DNL Voltage Divider Temperature Coefficient VW / T Code = 40H Full-Scale Error V WFSE Code = 7FH Zero-Scale Error VW Z S E Code = 00H RESISTOR TERMINALS Voltage Range4 Capacitance5 A, B Capacitance 5 W Shutdown Supply Current6 Shutdown Wiper Resistance Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Output Logic High Output Logic Low7 Input Current Input Capacitance5 POWER SUPPLIES Power Supply Range Power Supply Range Supply Current Supply Current Supply Current Power Dissipation8 Power Supply Sensitivity DYNAMIC CHARACTERISTICS5, 9, 10 Bandwidth 3 dB Bandwidth 3 dB Bandwidth 3 dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage VA, B, W C A, B CW IA_SD R W_SD ICM V IH VI L VO H V OL II L C IL VDD/VSS VDD ID D ID D IS S P DISS PSS PSS BW_10K BW_50K BW_100K THD W tS e N_WB
± 0.5 ± 0.1 5 0.5 +0.5
+1 +1 +0 +1 VD D
f = 1 MHz, Measured to GND, Code = 40H f = 1 MHz, Measured to GND, Code = 40H VA = VDD, VB = 0 V, SHDN = 0 VA = VDD, VB = 0 V, SHDN = 0, VDD = +15 V VA = VB = VW VDD = +5 V or +15 V VDD = +5 V or +15 V RL = 2.2 k to +5 V IOL = 1.6 mA, VLOGIC = +5 V, VDD = +15 V VIN = 0 V or +15 V 2.4
45 60 0.01 170 1
1 400
0.8 4.9 0.4 ±1 5
Dual Supply Range Single Supply Range, VSS = 0 VIH = +5 V or VIL = 0 V, VDD = +5 V VIH = +5 V or VIL = 0 V, VDD = +15 V VIH = +5 V or VIL = 0 V, VSS = 5 V or 15 V VIH = +5 V or VIL = 0 V, VDD = +15 V, VSS = 15 V VDD = +5 V ± 10%, or VSS = 5 V ± 10% VDD = +15 V ± 10% or VSS = 15 V ± 10% RAB = 10 k, Code = 40H RAB = 50 k, Code = 40H RAB = 100 k, Code = 40H VA = 1 V rms, VB = 0 V, f = 1 kHz VA = 10 V, VB = 0 V, ± 1 LSB Error Band RWB = 25 k, f = 1 kHz, RS = 0
± 4.5 4.5
± 16.5 28 0.0001 0.01 0.75 2 0.02 0.1 11 30 0.05 0.15 0.01 0.02 520 125 60 0.005 4 14
INTERFACE TIMING CHARACTERISTICS (Applies to All Parts [Notes 5, 11]) Input Clock Pulsewidth tCH, tCL Clock Level High or Low Data Setup Time t DS Data Hold Time t DH CLK to SDO Propagation Delay12 t PD RL = 2.2 k, CL < 20 pF CS Setup Time t CSS CS High Pulsewidth t CSW Reset Pulsewidth t RS CLK Rise to CS Rise Hold Time t CSH CS Rise to Clock Rise Setup t CS1
120 30 20 10 120 150 120 120 120
100
2
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AD7376
NOTES 11 Typicals represent average readings at +25°C, VDD = +15 V, and V SS = 15 V. 12 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 27. Test Circuit. 13 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 26. Test Circuit. 14 Resistor terminals A, B, W have no limitations on polarity with respect to each other. 15 Guaranteed by design and not subject to production test. 16 Measured at the A terminal. A terminal is open circuit in shutdown mode. 17 IOL = 200 µA for the 50 k version operating at V DD = +5 V. 18 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 19 Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 10 All dynamic characteristics use V DD = +15 V and V SS = 15 V. 11 See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 1 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. Switching characteristics are measured using both V DD = +5 V or +15 V. 12 Propagation delay depends on value of V DD, RL and CL see Applications section. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C, unless otherwise noted)
PIN CONFIGURATIONS PDIP & TSSOP-14
A1 B2 VSS 3 GND 4 CS 5 RS 6 CLK 7 14 W 13 NC A1 B2 VSS 3 GND 4
SOL-16
16 W 15 NC 14 VDD
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, +30 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, 16.5 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, +44 V VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD AX BX, AX WX, BX WX . . . . . . . . . . . . . . . . . . . ± 20 mA Digital Input Voltages to GND . . . . . . . . . . 0 V, VDD + 0.3 V Digital Output Voltage to GND . . . . . . . . . . . . . . 0 V, +30 V Operating Temperature Range . . . . . . . . . . . 40°C to +85°C Maximum Junction Temperature (TJ MAX) . . . . . . . +150°C Storage Temperature . . . . . . . . . . . . . . . . . . 65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C Package Power Dissipation . . . . . . . . . . . . (TJ MAX TA)/JA Thermal Resistance JA P-DIP (N-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W SOIC (SOL-16) . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C/W
AD7376
TOP VIEW (Not to Scale)
12 VDD 11 SDO 10 SHDN 9 SDI 8 NC
13 SDO TOP VIEW CS 5 (Not to Scale) 12 SHDN RS 6 11 SDI 10 NC 9 NC
AD7376
CLK 7 NC 8
NC = NO CONNECT
NC = NO CONNECT
ORDERING GUIDE
Model
k
Temperature Range
Package Description PDIP-14 SOL-16 TSSOP-14 PDIP-14 SOL-16 TSSOP-14 PDIP-14 SOL-16 TSSOP-14 PDIP-14 SOL-16 TSSOP-14
Package Options N-14 R-16 RU-14 N-14 R-16 RU-14 N-14 R-16 RU-14 N-14 R-16 RU-14
AD7376AN10 10 40°C to +85°C AD7376AR10 10 40°C to +85°C AD7376ARU10 10 40°C to +85°C AD7376AN50 50 40°C to +85°C AD7376AR50 50 40°C to +85°C AD7376ARU50 50 40°C to +85°C AD7376AN100 100 40°C to +85°C AD7376AR100 100 40°C to +85°C AD7376ARU100 100 40°C to +85°C AD7376AN1M 1,000 40°C to +85°C AD7376AR1M 1,000 40°C to +85°C AD7376ARU1M 1,000 40°C to +85°C Die Size: 101.6 mil × 127.6 mil, 2.58 mm × 3.24 mm Number Transistors: 840
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7376 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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3
AD7376Typical Performance Characteristics
100
PERCENT OF NOMINAL END-TO-END RESISTANCE % RAB
0.5 0.4 0.3
0.25 0.20
TA = 55 C TA = +25 C
R-DNL ERROR LSB
R-INL ERROR LSB
75
0.15 0.10 0.05 0 0.05 0.10 0.15 0.20 TA = +85 C TA = +25 C
0.2 0.1 0 0.1 0.2 0.3
TA = 55 C
50
TA = +85 C VDD = +15V VSS = 15V VA = 2.5V VB = 0V RAB = 50k
25 RWB 0 0 32 RWA 64 96 CODE Decimal 128
0.4 0.5 0 16 32
VDD = +15V VSS = 15V RAB = 50k 0 16 32 48 64 80 96 CODE Decimal 112 128
48 64 80 96 CODE Decimal
112 128
0.25
Figure 2. Wiper To End Terminal Percent Resistance vs. Code
Figure 3. Resistance Step Position Nonlinearity Error vs. Code
Figure 4. Relative Resistance Step Change from Ideal vs. Code
50
NOMINAL END-TO-END RESISTANCE k
14 01H 10H 20H 40H
1.5 I w = 100 A, TA = +25 C DATA = 40H 1.2
49
R_INL LSB
2
VDD = +15V VSS = 15V RAB = 50k NOMINAL
VWA V
12 10 8 6 4
48
0.9
47
46
2
CODE = 70H
TA = +25 C VDD = +15V VSS = 15V RAB = 50k 7FH
0.6
0.3
45 55 35 15
0
5 25 45 65 85 105 125 TEMPERATURE C
0
0.25
0.5 0.75 1 1.25 1.5 1.75 IWA mA
0 5 10 15 20 25 30 SUPPLY VOLTAGE (VDD - VSS) Volts
Figure 5. Nominal Resistance vs. Temperature
Figure 6. Resistance Linearity vs. Conduction Current
Figure 7. Resistance Nonlinearity Error vs. Supply Voltage
1.0 VA = 2.5V VB = 0V CODE = 40H RAB = 50k
20 15
000 900 RAB = 50k
WIPER CONTACT RESISTANCE
1
0.8
VWB/ T POTENTIOMETER MODE TEMPCO ppm/ C
10 5 0 5 10 15 20 25 VDD = +15V VSS = 15V VA = +2.5V VB = 0V 55 C < TA < +85 C RAB = 50k 16 32 48 64 80 96 CODE Decimal 112 128
800 700 600 500 400 300 200 100 0 55 35 15 VDD = +5V VSS = 5V VDD = +15V VSS = 15V 5 25 45 65 85 TEMPERATURE C 105 125 VDD = +5V VSS = 0V
INL LSB
0.6
0.4
0.2
0 5 10 15 20 25 30 SUPPLY VOLTAGE (VDD - VSS) Volts
30 0
Figure 8. Potentiometer Divider Nonlinearity Error vs. Supply Voltage
Figure 9. VWB/T Potentiometer Mode Tempco
Figure 10. Wiper Contact Resistance vs. Temperature
4
REV. 0
AD7376
0.25
INL NONLINEARITY ERROR LSB
0.25
40
0.20 0.15 0.10 0.05 0 0.05 0.10 0.15 0.20 0.25 0 VDD = +15V VSS = 15V VA = +2.5V VB = 0V RAB = 50k 16 32 TA = +25 C TA = 55 C
RHEOSTAT MODE TEMPCO ppm/ C
0.20 0.15 0.10
35 30 25 20 15 10 5 0 5 10 0 16 32
VDD = +15V VSS = 15V RAB = 50k
DNL LSB
0.05 0 0.05 0.10 VDD = +15V VSS = 15V VA = +2.5V VB = 0V RAB = 50k 0 16 32 48 64 80 96 CODE Decimal 112 128
TA = +85 C
0.15 0.20 112 128 0.25
48 64 80 96 CODE Decimal
48 64 80 96 CODE Decimal
112 128
Figure 11. Potentiometer Divider Nonlinearity Error vs. Code
Figure 12. Potentiometer Divider Differential Nonlinearity Error vs. Code
Figure 13. RWB/T Rheostat Mode Tempco
0 6 12
CODE = 7FH CODE = 40H CODE = 20H CODE = 10H
RAB = 10k
0 6 12
GAIN dB
CODE = 7FH CODE = 40H CODE = 20H CODE = 10H CODE = 08H CODE = 04H CODE = 02H CODE = 01H
A B W OP275
RAB = 1M
259.8
s
VDD = +15V VSS = --15V
GAIN dB
18 24 30 36 42 48 1k
A B
18 24 30 36 42
CODE = 08H CODE = 04H CODE = 02H CODE = 01H CODE = 00H
W OP275 VDD = +15V VSS = 15V VAMPL = 50mVrms
CODE = 3FH VA = 2.5V VB = 0V f = 100 kHz 50m
B Lw
40H
3FH
48
1M
VDD = +15V VSS = 15V VAMPL = 50mVrms RAB = 1M
HO5 s
5 S/DIV 100k
10k 100k FREQUENCY Hz
100
1k 10k FREQUENCY Hz
Figure 14. 10 k Gain vs. Frequency vs. Code
Figure 15. 1 M Gain vs. Frequency vs. Code
Figure 16. Midscale Transition Glitch
0 6 12
GAIN dB
CODE = 7FH RAB = 50k CODE = 40H 20H 10H AMP = 50mV VDD = +15V VSS = 15V RL = 1M A B
OP275
1.0
A2 12 CODE = 3FH VA = 12V VB = 0V f = 1 MHz VDD = +15V VSS = 15V THD % 1.6 V DLY
128kHz
27.08
s
0.1 NON-INVERTING MODE TEST CKT FIG 36 0.010
18 24 30 36 42 48
08H 04H 02H 01H
0
VDD = +15V VSS = 15V VA = 10V pp CODE = 40H RAB = 50k
5 0 5V 5V
B Lw
HO2 s
54 1k
2 S/DIV
0.001 0.0005 10
NON-INVERTING MODE TEST CKT FIG 35 100 1k 10k FREQUENCY Hz 200k
10k 100k FREQUENCY Hz
1M
Figure 17. 50 k Gain vs. Frequency vs. Code
Figure 18. Large Signal Settling Time
Figure 19. Total Harmonic Distortion Plus Noise vs. Frequency
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5
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