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Part: AD7450BRM
Category:
Data Conversion
-> ADC (Analog to Digital Converters)
-> 10-14 bit
-> 12 bit
Description: 3V/5 V, Differential Input, 1MSPS, 12-Bit ADC in SO-8 And SO-8
Company: Analog Devices
Datasheet: Download AD7450BRM datasheet File size : 464 kB
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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES Fast Throughput Rate: 1MSPS S p e c i f i e d for VDD of 3 V and 5 V Low Power at max Throughput Rate: 3 mW typ at 833kSPS with 3 V Supplies 8 mW typ at 1MSPS with 5 V Supplies Fully Differential Analog Input Wide Input Bandwidth: 7 0 d B SINAD at 300kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays H i g h Speed Serial Interface - SPI TM / Q S P I TM / M i c r o W i r e T M / DSP Compatible P o w e r d o w n Mode: 1µA max 8 Pin µSOIC and SOIC Packages APPLICATIONS Transducer Interface Battery Powered Systems Data Acquisition Systems Portable Instrumentation Motor Control Communications G E N E R A L DESCRIPTION
Differential Input, 1MSPS, 12-Bit ADC in µSO-8 and S0-8 AD7450
F U N C T I O N A L BLOCK DIAGRAM
V DD
VIN+ VINVREF
T/H
12-B IT S UCCESSIVE A PPROXIMATION A DC
S C LK
A D7450
CONTROL L OGIC
SDATA CS
G ND
The AD7450 is a 12-bit, high speed, low power, success i v e - a p p r o x i m a t i o n (SAR) analog-to-digital converter featuring a fully differential analog input. It operates from a single 3 V or 5 V power supply and features throughput rates up to 833kSPS or 1MSPS respectively. This part contains a low-noise, wide bandwidth, differential track and hold amplifier (T/H) which can handle input frequencies in excess of 1MHz with the -3dB point being 20MHz typically. The reference voltage for the AD7450 is applied externally to the VREF pin and can be varied from 100 mV to 2.5 V depending on the power supply and to suit the application. The value of the reference voltage determines the common mode voltage range of the part. With this truly differential input structure and variable reference input, the user can select a variety of input ranges and bias points. The conversion process and data acquisition are controlled using CS and the serial clock allowing the device to interface with Microprocessors or DSPs. The input signals are sampled on the falling edge of CS and the conversion is also initiated at this point.
MicroWire is a trademark of National Semiconductor Corporation. SPI and QSPI are trademarks of Motorola, Inc.
The SAR architecture of this part ensures that there are no pipeline delays. The AD7450 uses advanced design techniques to achieve very low power dissipation at high throughput rates.
P R O D U C T HIGHLIGHTS
1 . Operation with either 3 V or 5 V power supplies. 2 . High Throughput with Low Power Consumption. With a 3V supply, the AD7450 offers 3mW typ power consumption for 833kSPS throughput. 3 . Fully Differential Analog Input. 4 . F l e x i b l e Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the power to be reduced as the conversion time is reduced through the serial clock speed increase. This part also features a shutdown mode to maximize power efficiency at lower throughput rates. 5 . Variable Voltage Reference Input. 6 . N o Pipeline Delay. 7 . Accurate control of the sampling instant via a CS input and once off conversion control. 8. ENOB > 8 bits typ with 100mV Reference.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
AD7450 - SPECIFICATIONS
Parameter D Y N A M I C PERFORMANCE Signal to (Noise + Distortion) Ratio (SINAD)2 T o t a l Harmonic Distortion (THD) 2 Peak Harmonic or Spurious Noise2 I n t e r m o d u l a t i o n Distortion (IMD) 2 Second Order Terms T h i r d Order Terms A p e r t u r e Delay3 A p e r t u r e Jitter 3 Full Power Bandwidth3 Common Mode Rejection Ratio (CMRR)2 D C ACCURACY Resolution I n t e g r a l Nonlinearity (INL) 2 D i f f e r e n t i a l Nonlinearity (DNL) 2 Zero Code Error2 Positive Gain Error 2 N e g a t i v e Gain Error 2 A N A L O G INPUT Full Scale Input Span Absolute Input Voltage VIN+ V INDC Leakage Current Input Capacitance R E F E R E N C E INPUT VREF Input Voltage 70 -80 -80 -78 -78 10 50 20 2.5 TBD
1
( VDD = 2.7V to 3.3V, fSCLK = 15MHz, fS = 833kHz, VREF = 1.25 V; VDD = 4.75V to 5.25V, fSCLK = 18MHz, fS = 1MHz, VREF = 2.5 V; VCM 3 = VREF; TA = TMIN to TMAX, unless otherwise noted.)
Units Test Conditions/Comments FIN = 300kHz Sine Wave, fSAMPLE= 833kSPS, 1MSPS
A Version1 B Version1
70 -80 -80 -78 -78 10 50 20 2.5 TBD
dB min dB max dB max dB typ dB typ ns typ ps typ MHz typ MHz typ dB
@ -3 dB @ -0.1 dB
12 ±2 ±1 ±5 ±5 ±5
12 ±1 ±1 ±5 ±5 ±5 VIN+ - V I N -
Bits LSB LSB LSB LSB LSB Volts
max max max max max
Guaranteed No Missed Codes to 12 Bits.
2 x V REF 4 VC M = V REF VC M = V REF When in Track When in Hold 5 V supply (±1% tolerance for specified performance) 3 V supply (±1% tolerance for specified performance)
VCM3 ± VREF/2 VCM3 ± VREF/2 ±1 ±1 20 20 5 5 2.55 1.256 2.5 1.25 ±1 15 2.4 0.8 ±1 10
Volts Volts µ A max pF typ pF typ Volts Volts µ A max pF typ V min V max µ A max p F max V min V max µ A max p F max
DC Leakage Current VREF Input Capacitance LOGIC Input Input Input Input INPUTS High Voltage, VINH Low Voltage, VINL Current, IIN Capacitance, CIN7
±1 15 2.4 0.8 ±1 10
Typically 10 nA, VIN = 0 V or VDD
L O G I C OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL F l o a t i n g - S t a t e Leakage Current F l o a t i n g - S t a t e Output Capacitance7 O u t p u t Coding C O N V E R S I O N RATE Conversion Time T r a c k / H o l d Acquisition Time8 T h r o u g h p u t Rate 9
2.8 2.8 0.4 0.4 ±10 ±10 10 10 T w o ' s Complement 16 275 1 833 16 275 1 833
ISOURCE = 200µA ISINK =200µA
S C L K cycles 888ns with an 18MHz SCLK 1.07µs with a 15MHz SCLK ns max Sine Wave input M S P S max @ VDD = 5V k S P S max @ VDD = 3V
2
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PRELIMINARY TECHNICAL DATA
AD7450
Parameter P O W E R REQUIREMENTS V DD I DD8,10 N o r m a l Mode(Static) N o r m a l Mode (Operational) F u l l Power-Down Mode P o w e r Dissipation N o r m a l Mode (Operational) F u l l Power-Down A Version1 3/5 1 2.6 2 1 13 6 5 3 B Version1 3/5 1 2.6 2 1 13 6 5 3 Units Vmin/max mA typ m A max m A max µ A max m W max m W max µ W max µ W max Test Conditions/Comments Range: 3 V ± 10%; 5 V ± 5% VDD =3 V/5 V. SCLK On or Off VDD = 5 V. fSAMPLE=1MSPS VDD = 3 V. fSAMPLE=833kSPS SCLK On or Off VD D VD D VD D VD D =5 =3 =5 =3 V. V. V. V. fSAMPLE=1MSPS fSAMPLE=833kSPS SCLK On or Off SCLK On or Off
NOTES 1 T e m p e r a t u r e ranges as follows: A, B Versions: 40°C to +85°C. 2 S e e `Terminology' section. 3 C o m m o n Mode Voltage. The input signal can be centered on any choice s p e c i f i e d in Figure 8. 4 Because the input span of V IN+ and V IN- are both VREF, and they are 180° 5 T h e reference is functional from 100mV and for 5V supplies it can range 6 T h e reference is functional from 100mV and for 3V supplies it can range 7 S a m p l e tested @ +25°C to ensure compliance. 8 S e e POWER VERSUS THROUGHPUT RATE section. 8 T C O N V E R T + T Q U I E T (See `Serial Interface Section') 10 M e a s u r e d with a midscale DC input. S p e c i f i c a t i o n s subject to change without notice.
of dc Common Mode Voltage as long as this value is in the range out of phase, the differential voltage is 2 x V REF. up to TBDV (see `Reference Section'). up to 2.2V (see `Reference Section').
AD7450 - TIMING SPECIFICATIONS
Parameter f SCLK
4
1,2
( VDD = 2.7V to 3.3V, fSCLK = 15MHz, fS = 833kHz, VREF = 1.25 V; VDD = 4.75V to 5.25V, fSCLK = 18MHz, fS = 1MHz, VREF = 2.5 V; VCM 3 = VREF; TA = TMIN to TMAX, unless otherwise noted.)
Limit at TMIN, TMAX +3V +5V 10 15 16 x t SCLK 1.07 50 10 10 20 40 0 . 4 tS C L K 0 . 4 tS C L K 10 10 45 TBD 10 18 16 x t SCLK 0.88 50 10 10 20 40 0 . 4 tS C L K 0 . 4 tS C L K 10 10 45 TBD
Units k H z min M H z max µ s max ns min ns ns ns ns ns ns ns ns ns µs min min max max min min min min max max
Description
tCONVERT tQUIET t1 t2 t 35 t 45 t5 t6 t7 t 86 t POWER-UP7
tSCLK = 1/fSCLK S C L K = 15MHz, 18MHz Minimum Quiet Time between the End of a Serial Read and the Next Falling Edge of CS M i n i m u m CS Pulsewidth CS falling Edge to SCLK Falling Edge Setup Time Delay from CS Falling Edge Until SDATA 3-State Disabled Data Access Time After SCLK Falling Edge SCLK High Pulse Width SCLK Low Pulse Width SCLK Edge to Data Valid Hold Time SCLK Falling Edge to SDATA 3-State Enabled SCLK Falling Edge to SDATA 3-State Enabled Power-Up Time from Full Power-Down
NOTES 1 Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 Volts. 2 S e e Figure 1 and the "Serial Interface" section. 3 C o m m o n Mode Voltage. 4 M a r k / S p a c e ratio for the SCLK input is 40/60 to 60/40. 5 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V and time for an output to cross 0.4 V or 2.0 V for VDD = 3 V. 6 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured numb e r is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the t i m i n g characteristics is the true bus relinquish time of the part and is independent of the bus loading. 7 See `Power-up Time' Section. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA AD7450
t1
CS
t C ON VE RT t2 t5 1 2 3 4 5 t7 t3 t4 13
SC LK
B
14 t6 15 t8 16
t QU I ET
S DATA
0
0
0
0
D B 11
D B 10
DB2
DB1
DB0
3-STATE 4 LE ADI NG ZERO' S
Figure 1. Serial Interface Timing Diagram
A B S O L U T E MAXIMUM RATINGS 1
(TA = +25°C unless otherwise noted)
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 T r a n s i e n t currents of up to 100 mA will not cause SCR latch up.
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VIN+ to GND . . . . . . . . . . . . . . . . . 0.3 V to VDD + 0.3 V VIN- to GND . . . . . . . . . . . . . . . . . 0.3 V to VDD + 0.3 V Digital Input Voltage to GND . . . -0.3 V to VDD + 0.3 V Digital Output Voltage to GND . . -0.3 V to VDD + 0.3 V VREF to GND . . . . . . . . . . . . . . . . . . . -0.3 V to VDD +0.3 V Input Current to Any Pin Except Supplies2 . . . . ± 1 0 m A O p e r a t i n g Temperature Range Commercial (A, B Version) . . . . . . . . . -40oC to +85oC Storage Temperature Range . . . . . . . . . -65oC to +150oC J u n c t i o n Temperature . . . . . . . . . . . . . . . . . . . . . . . + 1 5 0 o C S O I C , µSOIC Package, Power Dissipation . . . . 4 5 0 m W JA Thermal Impedance . . . . . . . . . . 1 5 7 ° C / W (SOIC) 205.9°C/W (µSOIC) JC Thermal Impedance . . . . . . . . . . . 56°C/W (SOIC) 43.74°C/W (µSOIC) L e a d Temperature, Soldering Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . + 2 1 5 o C Infared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . + 2 2 0 o C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD
2 00µA
IOL
TO OU TP UT PIN CL 50 pF 2 00µA
+ 1.6 V
I OH
Figure 2. Load Circuit for Digital Output Timing Specifications
O R D E R I N G GUIDE
Model AD7450AR AD7450ARM AD7450BR AD7450BRM EVAL-AD7450CB2 E V A L - C O N T R O L BRD2 3
Range -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C E v a l u a t i o n Board C o n t r o l l e r Board
Linearity Error (LSB)1 ±2 ±2 ±1 ±1 LSB LSB LSB LSB
Package Option4 SO-8 RM-8 SO-8 RM-8
Branding Information AD7450AR CPA AD7450BR CPB
NOTES 1 Linearity error here refers to Integral Linearity Error. 2 This can be used as a stand-alone evaluation board or in conjunction with the EVALUATION BOARD CONTROLLER for evaluation/demonstration purposes. 3 E V A L U A T I O N BOARD CONTROLLER. This board is a complete unit allowing a PC to control and communicate with all Analog Devices e v a l u a t i o n boards ending in the CB designators. 4 S0 = SOIC; RM = µSOIC
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7450 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
4
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PRELIMINARY TECHNICAL DATA AD7450
P I N FUNCTION DESCRIPTION Pin No. Pin Mnemonic Function
1
V REF
2 3 4 5 6
VIN+ VINGND CS SDATA
7 8
SCLK VDD
Reference Input for the AD7450. An external reference must be applied to this input. For a 5 V power supply, the reference is 2.5 V (±1%) and for a 3 V power supply, the reference is 1.25 V (±1%) for specified performance. This pin should be decoupled to GND with a capacitor of at least 0.1µF. See the `Reference Section' for more details. Positive Terminal for Differential Analog Input. Negative Terminal for Differential Analog Input. Analog Ground. Ground reference point for all circuitry on the AD7450. All analog input signals and any external reference signal should be referred to this GND voltage. Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on the AD7450 and framing the serial data transfer. Serial Data. Logic Output. The conversion result from the AD7450 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists of four leading zeros followed by the 12 bits of conversion data which are provided MSB first. The output coding is two's complement. Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. T h i s clock input is also used as the clock source for the AD7450's conversion process. Power Supply Input. VDD is 3 V (±10%) or 5 V (±5%). This supply should be decoupled to GND with a 0.1µF Capacitor and a 10µF Tantalum Capacitor.
PIN CONFIGURATION SOIC and µSOIC
VREF VI N + VI N GND
1 2 3 4
8
VDD SCLK S DATA CS
AD7450 TOP VIEW
(Not to Scale)
7 6 5
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