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Part: AD7451
Category:
Description: Pseudo Differential Input, 1 Msps, 12-Bit A/D Converter in 8-Lead SOT-23
Company: Analog Devices
Datasheet: Download AD7451 datasheet File size : 464 kB
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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES Fast Throughput Rate: 1MSPS Specified for VDD of 2.7 V to 5.25 V L o w Power at max Throughput Rate: 3.75 mW typ at 1MSPS with VDD = 3 V 9 mW typ at 1MSPS with VDD = 5 V P s e u d o Differential Analog Input Wide Input Bandwidth: 7 0 d B SINAD at 300kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays H i g h Speed Serial Interface - SPI T M / Q S P I T M / M I C R O W I R E T M / DSP Compatible P o w e r - D o w n Mode: 1µA max 8 Pin SOT-23 and MSOP Packages APPLICATIONS T r a n s d u c e r Interface Battery Powered Systems Data Acquisition Systems Portable Instrumentation Motor Control Communications G E N E R A L DESCRIPTION
Pseudo Differential, 1MSPS, 12- & 10-Bit ADCs in 8-lead SOT-23 AD7451/AD7441
F U N C T I O N A L BLOCK DIAGRAM
VDD
VIN+ VINVREF
T/H
12-B IT SUCCESSIVE APPROXIMATION ADC
SCLK
A D7451/ A D7441
CONTROL LOGIC
SDATA +5
GND
The AD7451/AD7441 are respectively 12- and 10-bit, high speed, low power, successive-approximation (SAR) analog-to-digital converters that feature a pseudo differential analog input. These parts operate from a single 2.7 V to 5.25 V power supply and feature throughput rates up to 1MSPS. The parts contains a low-noise, wide bandwidth, differential track and hold amplifier (T/H) which can handle input frequencies in excess of 1MHz with the -3dB point being 20MHz typically. The reference voltage for the AD7451/AD7441 is applied externally to the VREF pin and can range from 100mV to 3.5 V. The conversion process and data acquisition are controlled using CS and the serial clock allowing the device to interface with Microprocessors or DSPs. The input signals are sampled on the falling edge of CS and the conversion is also initiated at this point. The SAR architecture of these parts ensures that there are no pipeline delays.
The AD7451/AD7441 use advanced design techniques to achieve very low power dissipation at high throughput rates.
P R O D U C T HIGHLIGHTS
1 . Operation with 2.7 V to 5.25 V power supplies. 2 . High Throughput with Low Power Consumption. With a 3V supply, the AD7451/AD7441 offer 3.75mW typ power consumption for a 1MSPS throughput rate. 3 . Pseudo Differential Analog Input. The VIN- input can be used as an offset from ground. 4 . F l e x i b l e Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the power to be reduced as the conversion time is reduced through the serial clock speed increase. These parts also feature a shutdown mode to maximize power efficiency at lower throughput rates. 5. Variable Voltage Reference Input 6 . N o Pipeline Delay. 7 . Accurate control of the sampling instant via a CS input and once off conversion control. 8. ENOB > 8-bits typically with 100mV reference.
MICROWIRE is a trademark of National Semiconductor Corporation. SPI and QSPI are trademarks of Motorola, Inc.
REV. PrE 5 March 03
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2003
AD7451 - SPECIFICATIONS1
Parameter D Y N A M I C PERFORMANCE Signal to (Noise + Distortion) (SINAD)2 T o t a l Harmonic Distortion (THD) 2 Peak Harmonic or Spurious Noise2 I n t e r m o d u l a t i o n Distortion (IMD) 2 Second Order Terms T h i r d Order Terms Aperture Delay 2 A p e r t u r e Jitter 2 Full Power Bandwidth2 D C ACCURACY Resolution I n t e g r a l Nonlinearity (INL) 2 D i f f e r e n t i a l Nonlinearity (DNL) 2 O f f s e t Error 2 G a i n Error 2 A N A L O G INPUT Full Scale Input Span Absolute Input Voltage VIN+ V IN-3 DC Leakage Current Input Capacitance R E F E R E N C E INPUT V REF Input Voltage DC Leakage Current VREF Input Capacitance L O G I C INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN5 L O G I C OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL F l o a t i n g - S t a t e Leakage Current F l o a t i n g - S t a t e Output Capacitance 5 O u t p u t Coding
PRELIMINARY TECHNICAL DATA
( VDD = 2.7V to 5.25V, fSCLK = 18MHz, fS = 1MSPS, VREF = 2.5 V; FIN = 300kHz; TA = TMIN to TMAX, unless otherwise noted.)
B Version1 Unit Test Conditions/Comments
-80dB typ -82dB typ
70 -75 -75 -85 -85 10 50 20 2.5 12 ±1
dB min dB max dB max dB typ dB typ ns typ ps typ MHz typ MHz typ Bits L S B max L S B max L S B max L S B max V V mV µ A max pF typ pF typ
@ -3 dB @ -0.1 dB
Guaranteed No Missed Codes to 12 Bits.
±1 ±3 ±3 VREF VREF ±100 ±1 20 6
VIN+ - V IN-
When in Track When in Hold ±1% tolerance for s p e c i f i e d performance
2.54 ±1 15 2.4 0.8 ±1 10 2.8 2.4 0.4 ±1 10 Straight (Natural) Binary 16 200 TBD 1
V µ A max pF typ V min V max µ A max p F max V min V min V max µ A max p F max
Typically 10nA, VIN = 0VorVDD
VDD = 5V; ISOURCE = 200µA VDD = 3V; ISOURCE = 200µA I S I N K =200µA
C O N V E R S I O N RATE Conversion Time T r a c k / H o l d Acquisition Time 2 Throughput Rate
888ns with an 18MHz SCLK Sine Wave Input Step Input
S C L K cycles ns max ns max MSPS max
REV. PrD
2
AD7451 - SPECIFICATIONS1
Parameter P O W E R REQUIREMENTS V DD I DD6,7 N o r m a l Mode(Static) N o r m a l Mode (Operational) F u l l Power-Down Mode P o w e r Dissipation N o r m a l Mode (Operational) F u l l Power-Down
PRELIMINARY TECHNICAL DATA
AD7451/AD7441
B Version1 2.7/5.25 Units Vmin/max mA typ m A max m A max µ A max m W max m W max µ W max µ W max
Test Conditions/Comments
SCLK On or Off VDD = 5 V. VDD = 3 V. SCLK On or Off V DD V DD VD D VD D =5 =3 =5 =3 V. V. V. SCLK On or Off V. SCLK On or Off
0.5 1.8 1.25 1 9 3.75 5 3
NOTES 1 T e m p e r a t u r e ranges as follows: B Versions: 40°C to +85°C. 2 S e e `Terminology' section. 3 A small DC input is applied to VIN- to provide a pseudo ground for VIN+ 4 The AD7451 is functional with a reference input in the range 100mV to 3.5 V . 5 S a m p l e tested @ +25°C to ensure compliance. 6 S e e POWER VERSUS THROUGHPUT RATE section. 7 M e a s u r e d with a midscale DC input. S p e c i f i c a t i o n s subject to change without notice.
AD7441 - SPECIFICATIONS1
Parameter D Y N A M I C PERFORMANCE Signal to (Noise + Distortion) (SINAD)2 T o t a l Harmonic Distortion (THD) 2 Peak Harmonic or Spurious Noise2 I n t e r m o d u l a t i o n Distortion (IMD) 2 Second Order Terms T h i r d Order Terms Aperture Delay 2 A p e r t u r e Jitter 2 Full Power Bandwidth2 D C ACCURACY Resolution I n t e g r a l Nonlinearity (INL) 2 D i f f e r e n t i a l Nonlinearity (DNL) 2 O f f s e t Error2 G a i n Error 2 A N A L O G INPUT Full Scale Input Span Absolute Input Voltage VIN+ V IN-3 DC Leakage Current Input Capacitance R E F E R E N C E INPUT VREF Input Voltage DC Leakage Current VREF Input Capacitance REV. PrD VIN+ - V IN-
( VDD = 2.7V to 5.25V, fSCLK = 18MHz, fS = 1MSPS, VREF = 2.5 V; FIN = 300kHz; TA = TMIN to TMAX, unless otherwise noted.)
B Version1 Unit
Test Conditions/Comments
-80dB typ -82dB typ
61 -73 -73 -78 -78 10 50 20 2.5 10 ±0.5
dB min dB max dB max dB typ dB typ ns typ ps typ MHz typ MHz typ Bits L S B max L S B max L S B max L S B max V V mV µ A max pF typ pF typ
@ -3 dB @ -0.1 dB
Guaranteed No Missed Codes to 10 Bits.
±0.5 ±3 ±3 VREF VREF ±100 ±1 20 6
When in Track When in Hold ± 1 % tolerance for specified performance
2.54 ±1 15
V µ A max pF typ
3
AD7441 - SPECIFICATIONS1
Parameter L O G I C INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN5 L O G I C OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL F l o a t i n g - S t a t e Leakage Current F l o a t i n g - S t a t e Output Capacitance 5 O u t p u t Coding
PRELIMINARY TECHNICAL DATA
AD7451/AD7441
B Version1 2.4 0.8 ±1 10 2.8 2.4 0.4 ±1 10 Straight (Natural) Binary 16 200 TBD 1 Unit V min V max µ A max p F max V min V min V max µ A max p F max
Test Conditions/Comments
Typically 10nA, VIN = 0VorVDD
VDD = 5V; ISOURCE = 200µA VDD = 3V; ISOURCE = 200µA I S I N K =200µA
C O N V E R S I O N RATE Conversion Time T r a c k / H o l d Acquisition Time 2 Throughput Rate P O W E R REQUIREMENTS V DD I DD6,7 N o r m a l Mode(Static) N o r m a l Mode (Operational) F u l l Power-Down Mode P o w e r Dissipation N o r m a l Mode (Operational) F u l l Power-Down
888ns with an 18MHz SCLK Sine Wave Input Step Input
S C L K cycles ns max ns max M S P S max
2.7/5.25 SCLK On or Off VDD = 5 V. VDD = 3 V. SCLK On or Off V DD V DD VD D VD D =5 =3 =5 =3 V. V. V. SCLK On or Off V. SCLK On or Off 0.5 1.8 1.25 1 9 3.75 5 3
Vmin/max mA typ m A max m A max µ A max m W max m W max µ W max µ W max
NOTES 1 T e m p e r a t u r e ranges as follows: B Versions: 40°C to +85°C. 2 S e e `Terminology' section. 3 A small DC input is applied to V IN- to provide a pseudo ground for V IN+ 4 T h e AD7441 is functional with a reference input in the range 100mV to 3.5 V 5 S a m p l e tested @ +25°C to ensure compliance. 6 S e e POWER VERSUS THROUGHPUT RATE section. 7 M e a s u r e d with a midscale DC input. S p e c i f i c a t i o n s subject to change without notice.
REV. PrD
4
PRELIMINARY TECHNICAL DATA
AD7451/AD7441 TIMING SPECIFICATIONS 1,2
Parameter fSCLK
4
AD7451/AD7441
( VDD = 2.7V to 5.25V, fSCLK = 18MHz, fS = 1MSPS, VREF = 2.5 V; FIN = 300kHz; TA = TMIN to TMAX, unless otherwise noted.)
Limit at T MIN , T M A X 10 18 16 x t SCLK 888 25 10 10 20 40 0.4 t SCLK 0.4 t SCLK 10 10 35 1
Units kHz min MHz max
Description
tCONVERT t QUIET t1 t2 t 35 t 45 t5 t6 t7 t 86 t POWER-UP7
tSCLK = 1/fSCLK ns max ns min ns ns ns ns ns ns ns ns ns µs min min max max min min min min max max Minimum Quiet Time between the End of a Serial Read and the Next Falling Edge of CS M i n i m u m CS Pulsewidth CS falling Edge to SCLK Falling Edge Setup Time Delay from CS Falling Edge Until SDATA 3-State Disabled Data Access Time After SCLK Falling Edge SCLK High Pulse Width SCLK Low Pulse Width SCLK Edge to Data Valid Hold Time SCLK Falling Edge to SDATA 3-State Enabled SCLK Falling Edge to SDATA 3-State Enabled Power-Up Time from Full Power-Down
NOTES 1 Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 Volts. 2 S e e Figure 1, Figure 2 and the `Serial Interface' section. 3 C o m m o n Mode Voltage. 4 M a r k / S p a c e ratio for the SCLK input is 40/60 to 60/40. 5 Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.4 V with V DD = 5 V and time for an output to cross 0.4 V or 2.0 V for VDD = 3 V. 6 t 8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured numb e r is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 8, quoted in the t i m i n g characteristics is the true bus relinquish time of the part and is independent of the bus loading. 7 See `Power-up Time' Section. Specifications subject to change without notice.
t1
+5
t CO N VERT t2 t5 1 2 3 4 5 t7 13
SC LK
B
14 t6 15 t8 16
t3
t4 0 0 0 DB 11
t Q UIET
SDATA
0
DB 10
DB 2
DB 1
D B0
4 LE AD IN G ZE RO'S
3-STATE
Figure 1. AD7451 Serial Interface Timing Diagram
t1
+5
t CO NV ERT t2 t5 1 2 3 4 5 t7 13
SC LK
B
14 t6 15 t8 16
t3
t4 0 0 0 D B9
t QU IE T
SDATA
0
D B8
D B0
0
0
4 LEA DING ZERO 'S
2 T RA IL IN G ZE ROS
3-STATE
REV. PrD
Figure 2. AD7441 Serial Interface Timing Diagram 5
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