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Part: AD7452BRM
Category:
Description: Differential Input, 555 Ksps, 12-Bit A/D Converter in 8-Lead SOT-23
Company: Analog Devices
Datasheet: Download AD7452BRM datasheet File size : 464 kB
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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES Specified for VDD of 3 V and 5 V L o w Power at max Throughput Rate: 7 . 2 5 mW max at 555kSPS with 3 V Supplies 3 . 3 mW max at 555kSPS with 5 V Supplies F u l l y Differential Analog Input Wide Input Bandwidth: 7 0 d B SINAD at 100kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays H i g h Speed Serial Interface - SPI T M / Q S P I T M / M I C R O W I R E T M / DSP Compatible P o w e r - D o w n Mode: 1µA max 8 Lead SOT-23 and MSOP Packages APPLICATIONS T r a n s d u c e r Interface Battery Powered Systems Data Acquisition Systems Portable Instrumentation Motor Control Communications G E N E R A L DESCRIPTION
Differential Input, 555kSPS, 12-Bit ADC in an 8-lead SOT-23 AD7452
F U N C T I O N A L BLOCK DIAGRAM
VDD
VIN+ VINVREF
T/H
12-B IT SUCCESSIVE APPROXIMATION ADC
SCLK
A D7452
CONTROL LOGIC
SDATA +5
GND
The AD7452 is a 12-bit, low power, successive-approximation (SAR) analog-to-digital converter that features a fully differential analog input. This part operates from a single 3 V or 5 V power supply and features throughput rates up to 555kSPS. The part contains a low-noise, wide bandwidth, differential track and hold amplifier (T/H) which can handle input frequencies in excess of 1MHz. The reference voltage is applied externally to the VREF pin and can be varied from 100 mV to 3.5 V depending on the power supply and what suits the application. The value of the reference voltage determines the common mode voltage range of the part. With this truly differential input structure and variable reference input, the user can select a variety of input ranges and bias points. The conversion process and data acquisition are controlled using CS and the serial clock allowing the device to interface with Microprocessors or DSPs. The input signals are sampled on the falling edge of CS and the conversion is also initiated at this point.
The SAR architecture of these parts ensures that there are no pipeline delays. The AD7452 uses advanced design techniques to achieve very low power dissipation.
P R O D U C T HIGHLIGHTS
1 . Operation with either 3 V or 5 V power supplies. 2 . Low Power Consumption. With a 3V supply, the AD7452 offers 3.3 mW max power consumption for 555kSPS throughput. 3 . Fully Differential Analog Input. 4 . F l e x i b l e Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the power to be reduced as the conversion time is reduced through the serial clock speed increase. These parts also feature a shutdown mode to maximize power efficiency at lower throughput rates. 5 . Variable Voltage Reference Input. 6 . N o Pipeline Delay. 7 . Accurate control of the sampling instant via a CS input and once off conversion control. 8. ENOB > 8 Bits typically for a 100mV reference.
MICROWIRE is a trademark of National Semiconductor Corporation. SPI and QSPI are trademarks of Motorola, Inc.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2003
AD7452 - SPECIFICATIONS
Parameter D Y N A M I C PERFORMANCE Signal to (Noise + Distortion) (SINAD)3 T o t a l Harmonic Distortion (THD) 3 Peak Harmonic or Spurious Noise3 I n t e r m o d u l a t i o n Distortion (IMD) 3 Second Order Terms T h i r d Order Terms Aperture Delay 3 A p e r t u r e Jitter 3 Full Power Bandwidth3 D C ACCURACY Resolution I n t e g r a l Nonlinearity (INL) 3 D i f f e r e n t i a l Nonlinearity (DNL) 3 Zero Code Error 3 P o s i t i v e Gain Error 3 N e g a t i v e Gain Error 3 A N A L O G INPUT Full Scale Input Span Absolute Input Voltage VIN+ V INDC Leakage Current Input Capacitance R E F E R E N C E INPUT V REF Input Voltage VD D VD D VD D VD D VD D VD D fa =
PRELIMINARY TECHNICAL 3.6V, f = 10MHz, f DATA ( V = 2.7V to
1
Test Conditions/Comments F IN = 100kHz = 4.75V to 5.25V = 2.7V to 3.6V = 4.75V to 5.25V, -80dB typ = 2.7V to 3.6V, -78dB typ = 4.75V to 5.25V, -82dB typ = 2.7V to 3.6V, -80dB typ 90kHz, fb = 110kHz 70 68 -75 -73 -75 -73 -83 -83 5 50 20 2.54 12 ±1 Guaranteed No Missed Codes to 12 Bits. VDD = 4.75V to 5.25V VDD = 2.7V to 3.6V VDD = 4.75V to 5.25V VDD = 2.7V to 3.6V VDD = 4.75V to 5.25V VDD = 2.7V to 3.6V 2 x V REF 5 VCM2 = VREF VCM2 = VREF When in Track/Hold VDD = 4.75V to 5.25V (±1% tolerance for specified performance) VDD = 2.7V to 3.6V (±1% tolerance for specified performance) W h e n in Track/Hold ±1 ±3 ±6 ±3 ±6 ±3 ±6 V I N + - VI N VCM2 ± VREF/2 VCM2 ± VREF/2 ±1 30/10 dB dB dB dB dB dB B Version1 U n i t
DD SCLK S = 555kSPS, VREF = 2.0 V; VDD = 4.75V to 5.25V, fSCLK = 10MHz, fS = 555kSPS, VREF = 2.5 V; VCM 2 = VREF; TA = TMIN to TMAX, unless otherwise noted.)
min min max max max max
@ -3 dB @ -0.1 dB
dB typ dB typ ns typ ps typ MHz typ MHz typ Bits L S B max LSB LSB LSB LSB LSB LSB LSB V V V µ A max pF typ max max max max max max max
2.56 2.07 ±1 10/30 2.4 0.8 ±1 10
V V µ A max pF typ V min V max µ A max p F max
DC Leakage Current VREF Input Capacitance L O G I C INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN8 L O G I C OUTPUTS Output High Voltage, VOH
Typically 10nA, VIN = 0VorVDD
Output Low Voltage, VOL F l o a t i n g - S t a t e Leakage Current F l o a t i n g - S t a t e Output Capacitance 8 O u t p u t Coding
VDD = 4.75V to 5.25V; ISOURCE = 200µA VDD = 2.7V to 3.6V; ISOURCE = 200µA I S I N K =200µA
2.8 2.4 0.4 ±1 10 Two's Complement
V min V min V max µ A max p F max
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PRELIMINARY TECHNICAL DATA
AD7452 - SPECIFICATIONS1
Parameter C O N V E R S I O N RATE Conversion Time T r a c k / H o l d Acquisition Time 3 Throughput Rate P O W E R REQUIREMENTS V DD I D D 9 , 10 N o r m a l Mode(Static) N o r m a l Mode (Operational) F u l l Power-Down Mode P o w e r Dissipation N o r m a l Mode (Operational) F u l l Power-Down Test Conditions/Comments 1.6µs with an 10MHz SCLK Sine Wave Input Step Input B Version1 16 200 290 555 Units S C L K cycles ns max ns max k S P S max
R a n g e : 3 V+20%/-10%; 5 V ± 5% SCLK On or Off VDD = 4.75V to 5.25V. VDD = 2.7V to 3.6V. SCLK On or Off VD D VD D VD D VD D =5 =3 =5 =3 V. V. V. V. 1.55mW typ for 100kSPS 0.64mW typ for 100kSPS SCLK On or Off SCLK On or Off
2.7/5.25 0.5 1.5 1.2 1 7.25 3.3 5 3
Vmin/max mA typ m A max m A max µ A max m W max m W max µ W max µ W max
NOTES 1 T e m p e r a t u r e ranges as follows: B Version: 40°C to +85°C. 2 C o m m o n Mode Voltage. The input signal can be centered on any choice of dc Common Mode Voltage as long as this value is in the range specified in Figures 8 and 9. 3 S e e `Terminology' section. 4 F o r input frequencies above 2.5MHz, a correct conversio result cannot be guaranteed 5 Because the input spans of V IN+ and V IN- are both V REF, and they are 180° out of phase, the differential voltage is 2 x VREF. 6 T h e AD7452 is functional with a reference input from100mV and for V DD = 5V, the reference can range up to 3.5V. 7 T h e AD7452 is functional with a reference input from100mV and for V DD = 3V, the reference range up to 2.2V. 8 S a m p l e tested @ +25°C to ensure compliance. 9 S e e Power vs. Throughput Rate section. 10 M e a s u r e d with a midscale DC input. S p e c i f i c a t i o n s subject to change without notice.
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PRELIMINARY TECHNICAL DATA
AD7452 TIMING SPECIFICATIONS 1,2
Parameter fSCLK
4
( VDD = 2.7V to 3.6V, fSCLK = 10MHz, fS = 555kSPS, VREF = 2.0 V; VDD = 4.75V to 5.25V, fSCLK = 10MHz, fS = 555kSPS, VREF = 2.5 V; VCM 3 = VREF; TA = TMIN to TMAX, unless otherwise noted.)
Limit at T MIN , T M A X 10 10 16 x t SCLK 1.6 60 10 10 20 40 0.4 t SCLK 0.4 t SCLK 10 10 35 1
Units k H z min M H z max
Description
tCONVERT t QUIET t1 t2 t 35 t 45 t5 t6 t7 t 86 t POWER-UP7
tSCLK = 1/fSCLK µ s max ns min ns ns ns ns ns ns ns ns ns µs min min max max min min min min max max Minimum Quiet Time between the End of a Serial Read and the Next Falling Edge of CS M i n i m u m CS Pulsewidth CS falling Edge to SCLK Falling Edge Setup Time Delay from CS Falling Edge Until SDATA 3-State Disabled Data Access Time After SCLK Falling Edge SCLK High Pulse Width SCLK Low Pulse Width SCLK Edge to Data Valid Hold Time SCLK Falling Edge to SDATA 3-State Enabled SCLK Falling Edge to SDATA 3-State Enabled Power-Up Time from Full Power-Down
NOTES 1 Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 Volts. 2 S e e Figure 1 and the `Serial Interface' section. 3 C o m m o n Mode Voltage. 4 M a r k / S p a c e ratio for the SCLK input is 40/60 to 60/40. 5 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with V DD = 5 V and time for an output to cross 0.4 V or 2.0 V for VDD = 3 V. 6 t 8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured numb e r is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 8, quoted in the t i m i n g characteristics is the true bus relinquish time of the part and is independent of the bus loading. 7 See `Power-up Time' Section. Specifications subject to change without notice.
t1 +5 t t2
CONVERT B 5 t7 13 14 t6 15 16
SCLK
1 2 3 4
t5
t3
t4
t8
t QUIET
SDATA
0
0
0
0
DB11
DB10
DB2
DB1
DB0
4 LEADING ZERO'S
3-ST TE A
Figure 1. AD7452 Serial Interface Timing Diagram
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PRELIMINARY TECHNICAL DATA AD7452
A B S O L U T E MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VIN+ to GND . . . . . . . . . . . . . . . . . 0.3 V to VDD + 0.3 V 0.3 V to VDD + 0.3 V VIN- to GND . . . . . . . . . . . . . . . Digital Input Voltage to GND . . . . . . . . -0.3 V to +7 V Digital Output Voltage to GND . -0.3 V to VDD + 0.3 V VREF to GND . . . . . . . . . . . . . . . . . -0.3 V to VDD +0.3 V Input Current to Any Pin Except Supplies2 . . . . ± 1 0 m A O p e r a t i n g Temperature Range C o m m e r c i a l (B Version) . . . . . . . . . . . -40oC to +85oC Storage Temperature Range . . . . . . . . . -65oC to +150oC J u n c t i o n Temperature . . . . . . . . . . . . . . . . . . . . . . . + 1 5 0 o C JA Thermal Impedance . . . . . . . . . . 2 0 5 . 9 ° C / W (MSOP) 211.5°C/W (SOT-23) JC Thermal Impedance . . . . . . . . . 43.74°C/W (MSOP) 91.99°C/W (SOT-23) L e a d Temperature, Soldering Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . + 2 1 5 o C Infared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . + 2 2 0 o C E S D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kV
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 T r a n s i e n t currents of up to 100 mA will not cause SCR latch up.
2 00µA
IOL
TO OUTP UT PIN CL 50 pF 2 00µA
+ 1.6 V
IOH
Figure 2. Load Circuit for Digital Output Timing Specifications
O R D E R I N G GUIDE
Model AD7452BRT AD7452BRM EVAL-AD7452CB E V A L - C O N T R O L BRD2 3
Range -40°C to +85°C -40°C to +85°C E v a l u a t i o n Board C o n t r o l l e r Board
Linearity Error (LSB)1 ± 1 LSB ± 1 LSB
Package Option4 RT-8 RM-8
Branding Information C07 C07
NOTES 1 L i n e a r i t y error here refers to Integral Non-linearity Error. 2 This can be used as a stand-alone evaluation board or in conjunction with the EVALUATION BOARD CONTROLLER for evaluation/demonstration purposes. 3 E V A L U A T I O N BOARD CONTROLLER. This board is a complete unit allowing a PC to control and communicate with all Analog Devices e v a l u a t i o n boards ending in the CB designators. To order a complete Evaluation Kit, you will need to order the ADC evaluation board i.e. E V A L - A D 7 4 5 2 C B , the EVAL-CONTROL BRD2 and a 12V AC transformer. See the EVAL-AD7452CB technote for more information. 4 R T = SOT-23; RM = MSOP
CAUTION E S D (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V r e a d i l y accumulate on the human body and test equipment and can discharge without d e t e c t i o n . Although the AD7452 features proprietary ESD protection circuitry, p e r m a n e n t damage may occur on devices subjected to high-energy electrostatic d i s c h a r g e s . Therefore, proper ESD precautions are recommended to avoid performance d e g r a d a t i o n or loss of functionality.
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