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Part: AD7457BRM
Category:
Description: Pseudo Differential Input, 100 Ksps, 12-Bit ADC in 8-Lead SOT-23
Company: Analog Devices
Datasheet: Download AD7457BRM datasheet File size : 464 kB
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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES Specified for VDD of 3 V and 5 V V e r y Low Power: TBD mW typ at 100kSPS with 3 V Supplies TBD mW typ at 100kSPS with 5 V Supplies P s e u d o Differential Analog Input W i d e Input Bandwidth: 7 0 d B SINAD at 20kHz Input Frequency N o Pipeline Delays S e r i a l Interface - SPI T M / Q S P I T M / M I C R O W I R E T M / D S P Compatible A u t o m a t i c Power-Down Mode 8 Pin SOT-23 and µSOIC Package APPLICATIONS T r a n s d u c e r Interface Battery Powered Systems Data Acquisition Systems Portable Instrumentation Motor Control Communications
Pseudo Differential, 100kSPS, 12-Bit ADC in 8-lead SOT-23 AD7457
F U N C T I O N A L BLOCK DIAGRAM
VDD
VIN+ VINVREF
T/H
12-B IT SUCCESSIVE A PPROXIMATION A DC
SCLK
AD7457
CONTROL L OGIC
SDATA +5
GND
G E N E R A L DESCRIPTION
The AD7457 is a 12-bit, low power, successive-approximation (SAR) analog-to-digital converter that features a pseudo differential analog input. The part operates from a single 2.7 V to 5.25 V power supply and features throughput rates up to 100kSPS. The part contains a low-noise, wide bandwidth, differential track and hold amplifier (T/H) which can handle input frequencies in excess of 1MHz with the -3dB point being 20MHz typically. The reference voltage is 2.5 V and is applied externally to the VREF pin. The conversion process and data acquisition are controlled using CS and the serial clock allowing the device to interface with Microprocessors or DSPs. The device is powered up on the falling edge of CS and a conversion is initiated on the rising edge of CS, where the analog input is sampled. Once a conversion is complete, the device automatically enters a power down mode to reduce power dissipation between conversions.
The SAR architecture of this part ensures that there are no pipeline delays.
PRODUCT HIGHLIGHTS
1 . Operation with 2.7 V to 5.25 V power supplies. 2 . Low Power Consumption. With a 3V supply, the AD7457 offers 1mW typ power consumption for 100kSPS throughput. 3 . Pseudo Differential Analog Input. The VIN- input can be used as an offset from ground 4 . N o Pipeline Delay. 5 . Accurate control of the sampling instant via a CS input and once off conversion control. 6 . 8 - l e a d SOT-23 package.
MICROWIRE is a trademark of National Semiconductor Corporation. SPI and QSPI are trademarks of Motorola, Inc.
REV. PrA 24/07/02
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002
AD7457 - SPECIFICATIONS1
Parameter D Y N A M I C PERFORMANCE Signal to (Noise + Distortion) (SINAD)2 T o t a l Harmonic Distortion (THD) 2 Peak Harmonic or Spurious Noise2 I n t e r m o d u l a t i o n Distortion (IMD) 2 Second Order Terms T h i r d Order Terms Aperture Delay 2 A p e r t u r e Jitter 2 Full Power Bandwidth2 D C ACCURACY Resolution I n t e g r a l Nonlinearity (INL) 2 D i f f e r e n t i a l Nonlinearity (DNL) 2 O f f s e t Error 2 G a i n Error 2 A N A L O G INPUT Full Scale Input Span Absolute Input Voltage VIN+ V IN-3 DC Leakage Current Input Capacitance R E F E R E N C E INPUT V REF Input Voltage DC Leakage Current VREF Input Capacitance L O G I C INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN7 L O G I C OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL F l o a t i n g - S t a t e Leakage Current F l o a t i n g - S t a t e Output Capacitance 7 O u t p u t Coding
PRELIMINARY TECHNICAL DATA
( VDD = 2.7V to 5.25V, fSCLK = 12MHz, fS = 100kHz, VREF = 2.5 V; FIN = 20kHz; TA = TMIN to TMAX, unless otherwise noted.)
B Version1 Unit Test Conditions/Comments
-80dB typ -82dB typ
70 -75 -75 -85 -85 10 50 20 2.5 12 ±1
dB min dB max dB max dB typ dB typ ns typ ps typ MHz typ MHz typ Bits L S B max L S B max L S B max L S B max V V V µ A max pF typ pF typ
@ -3 dB @ -0.1 dB
Guaranteed No Missed Codes to 12 Bits.
±1 ±3 ±3 VREF VREF 0.1 to 1 ±1 20 6
VIN+ - VIN
-
When in Track When in Hold ± 1 % tolerance for specified performance
2.5 ±1 15 2.4 0.8 ±1 10 2.8 2.4 0.4 ±1 10 Straight (Natural) Binary
V µ A max pF typ V min V max µ A max p F max V min V min V max µ A max p F max
Typically 10nA, VIN = 0VorVDD
VDD = 5V; ISOURCE = 200µA VDD = 3V; ISOURCE = 200µA I S I N K =200µA
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PRELIMINARY TECHNICAL DATA
AD7457 - SPECIFICATIONS
Parameter C O N V E R S I O N RATE Conversion Time T r a c k / H o l d Acquisition Time 2 T h r o u g h p u t Rate 6 P O W E R REQUIREMENTS V DD I DD5, 7 Static Operational P o w e r Dissipation Operational Test Conditions/Comments 1.33µs with a 12MHz SCLK Sine Wave Input Step Input B Version1 16 TBD TBD 100 Units
AD7457
S C L K cycles ns max ns max k S P S max
2.7/5.25 VDD =3 V/5 V. SCLK On or Off VDD = 5 V. VDD = 3 V. VDD =5 V. VDD =3 V. 0.5 TBD TBD TBD TBD
Vmin/max mA typ m A max m A max m W max m W max
NOTES 1 T e m p e r a t u r e ranges as follows: A, B Versions: 40°C to +85°C. 2 S e e `Terminology' section. 3 A small DC input is applied to V IN- to provide a pseudo ground for V IN+. 4 S a m p l e tested @ 25°C to ensure compliance. 5 S e e Power vs Throughput rate section. 6 S e e Serial Interface section 7 M e a s u r e d with a midscale DC input. S p e c i f i c a t i o n s subject to change without notice.
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PRELIMINARY TECHNICAL DATA
AD7457 TIMING SPECIFICATIONS 1,2
Parameter fSCLK
4
( VDD = 2.7V to 5.25V, fSCLK = 12MHz, fS = 100kHz, VREF = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.)
Limit at TMIN, TMAX 10 12 16 x t SCLK 1.33 1.4 1.4 10 20 40 0.4 t SCLK 0.4 t SCLK 10 10 35 20
Units k H z min M H z max µs µs µs ns ns ns ns ns ns ns ns ns max min min min max max min min min min max min
Description
tCONVERT tPOWERUP t ACQUISITION t2 t 35 t 45 t5 t6 t7 t 86 t SLEEP
tSCLK = 1/fSCLK 1 2 M H z f SCLK P o w e r - U p Time A c q u i s i t i o n Time CS Rising Edge to SCLK Falling Edge Setup Time Delay from CS Rising Edge Until SDATA 3-State Disabled Data Access Time After SCLK Falling Edge SCLK High Pulse Width SCLK Low Pulse Width SCLK Edge to Data Valid Hold Time SCLK Falling Edge to SDATA 3-State Enabled SCLK Falling Edge to SDATA 3-State Enabled Time spent in Power Down
NOTES 1 Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 Volts. 2 S e e Figure 1 and the `Serial Interface' section. 3 C o m m o n Mode Voltage. 4 M a r k / S p a c e ratio for the SCLK input is 40/60 to 60/40. 5 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with V DD = 5 V and time for an output to cross 0.4 V or 2.0 V for VDD = 3 V. 6 t 8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured numb e r is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 8, quoted in the t i m i n g characteristics is the true bus relinquish time of the part and is independent of the bus loading. S p e c i f i c a t i o n s subject to change without notice.
POW ER UP
C ON VE RT STA RT
TR AC K TPOWERUP
H OLD
TR AC K
TPOWERUP
TACQU IS IT IO N
+5
T AC QU IS ITIO N
AUTO M AT IC POW ER DOW N
t2
t5
SC LK
t4
t7
t3
SDATA
t6
t8
TS LE EP
0
T HR EE-S TATE
0
0
0
DB11 DB10
D B2
D B1
DB 0
THR EE -S TATE
4 L EAD ING Z ERO 'S
Figure 1. AD7457 Serial Interface Timing Diagram
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PRELIMINARY TECHNICAL DATA AD7457
A B S O L U T E MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
2 00µA IOL
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VIN+ to GND . . . . . . . . . . . . . . . . . 0.3 V to VDD + 0.3 V 0.3 V to VDD + 0.3 V VIN- to GND . . . . . . . . . . . . . . . Digital Input Voltage to GND . . . . . . . . -0.3 V to +7 V Digital Output Voltage to GND . -0.3 V to VDD + 0.3 V VREF to GND . . . . . . . . . . . . . . . . . -0.3 V to VDD +0.3 V Input Current to Any Pin Except Supplies2 . . . . ± 1 0 m A O p e r a t i n g Temperature Range Commercial (A, B Version) . . . . . . . . . -40oC to +85oC Storage Temperature Range . . . . . . . . . -65oC to +150oC J u n c t i o n Temperature . . . . . . . . . . . . . . . . . . . . . . . + 1 5 0 o C JA Thermal Impedance . . . . . . . . . . 2 0 5 . 9 ° C / W (µSOIC) 211.5°C/W (SOT-23) JC Thermal Impedance . . . . . . . . 43.74°C/W (µSOIC) 91.99°C/W (SOT-23) L e a d Temperature, Soldering Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . + 2 1 5 o C Infared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . + 2 2 0 o C E S D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5kV
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 T r a n s i e n t currents of up to 100 mA will not cause SCR latch up.
TO OU TP UT PIN CL 50 pF 2 00µA
+ 1.6 V
IO H
Figure 2. Load Circuit for Digital Output Timing Specifications
O R D E R I N G GUIDE
Model AD7457BRT AD7457BRM TBD2 E V A L - C O N T R O L BRD2 3
Range -40°C to +85°C -40°C to +85°C E v a l u a t i o n Board C o n t r o l l e r Board
Linearity Error (LSB)1 ± 1 LSB ± 1 LSB
Package Option4 RT-8 RM-8
Branding Information C0D C0D
NOTES 1 L i n e a r i t y error here refers to Integral Non-linearity Error. 2 This can be used as a stand-alone evaluation board or in conjunction with the EVALUATION BOARD CONTROLLER for evaluation/demonstration purposes. 3 E V A L U A T I O N BOARD CONTROLLER. This board is a complete unit allowing a PC to control and communicate with all Analog Devices e v a l u a t i o n boards ending in the CB designators. To order a complete Evaluation Kit, you will need to order the ADC evaluation board i.e. T B D , the EVAL-CONTROL BRD2 and a 12V AC transformer. See the TBD technote for more information. 4 S0 = SOIC; RM = µSOIC
CAUTION E S D (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V r e a d i l y accumulate on the human body and test equipment and can discharge without d e t e c t i o n . Although the AD7457 features proprietary ESD protection circuitry, p e r m a n e n t damage may occur on devices subjected to high-energy electrostatic d i s c h a r g e s . Therefore, proper ESD precautions are recommended to avoid performance d e g r a d a t i o n or loss of functionality.
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