|
Details, datasheet, quote on part number:AD7538AQ
| |
Datasheet text preview:
a
FEATURES All Grades 14-Bit Monotonic Over the Full Temperature Range Low Cost 14-Bit Upgrade for 12-Bit Systems 14-Bit Parallel Load with Double Buffered Inputs Small 24-Pin, 0.3 DIP and SOIC Low Output Leakage (<20 nA) Over the Full Temperature Range APPLICATIONS Microprocessor Based Control Systems Digital Audio Precision Servo Control Control and Measurement in High Temperature Environments
LC2MOS P-Compatible 14-Bit DAC AD7538
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7538 is a 14-bit monolithic CMOS D/A converter which uses laser trimmed thin-film resistors to achieve excellent linearity. The DAC is loaded by a single 14-bit wide word using standard Chip Select and Memory Write Logic. Double buffering, which is optional using LDAC, allows simultaneous update in a system containing multiple AD7538s. A novel low leakage configuration (U.S. Patent No. 4,590,456) enables the AD7538 to exhibit excellent output leakage current characteristics over the specified temperature range. The AD7538 is manufactured using the Linear Compatible CMOS (LC2MOS) process. It is speed compatible with most microprocessors and accepts TTL or CMOS logic level inputs.
1. Guaranteed Monotonicity The AD7538 is guaranteed monotonic to 14-bits over the full temperature range for all grades. 2. Low Cost The AD7538, with its 14-bit dynamic range, affords a low cost solution for 12-bit system upgrades. 3. Small Package Size The AD7538 is packaged in a small 24-pin, 0.3" DIP and a 24-pin SOIC. 4. Low Output Leakage By tying VSS (Pin 24) to a negative voltage, it is possible to achieve a low output leakage current at high temperatures. 5. Wide Power Supply Tolerance The device operates on a +12 V to +15 V VDD, with a ± 5% tolerance on this nominal figure. All specifications are guaranteed over this range.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD7538SPECIFICATIONS1 (VV
Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Full-Scale Error + 2 5° C TMIN to TMAX Gain Temperature Coefficient3; Gain/Temperature Output Leakage Current IOUT (Pin 3) + 2 5° C TMIN to TMAX TMIN to TMAX REFERENCE INPUT Input Resistance, Pin 1 J, K Versions 14 ±2 ±1 ±4 ±8 ±2 ±5 ± 10 ± 25 3.5 10 14 ±1 ±1 ±4 ±5 ±2 ±5 ± 10 ± 25 3.5 10
= +11.4 V to +15.75 V2, VREF = +10 V; VPIN3 = VPIN4 = 0 V, SS = 300 mV. All specifications TMIN to TMAX unless otherwise noted.)
DD
A, B Versions
S Version
T Version
Units
Test Conditions/Comments
14 ±2 ±1 ±4 ± 10 ±2 ±5 ± 20 ± 150 3.5 10
14 ±1 ±1 ±4 ±6 ±2 ±5 ± 20 ± 150 3.5 10
Bits LSB max LSB max LSB max LSB max ppm/°C typ nA max nA max nA max k min k max V min V max µA max µA max pF max
All Grades Guaranteed Monotonic Over Temperature. Measured Using Internal RFB DAC Registers Loaded with All 1s.
All Digital Inputs 0 V VSS = 300 mV V SS = 0 V Typical Input Resistance = 6 k
DIGITAL INPUTS VIH (Input High Voltage) VIL (Input Low Voltage) IIN (Input Current) + 2 5° C TMIN to TMAX CIN (Input Capacitance)3 POWER SUPPLY VDD Range VSS Range IDD
2.4 0.8 ±1 ± 10 7
2.4 0.8 ±1 ± 10 7
2.4 0.8 ±1 ± 10 7
2.4 0.8 ±1 ± 10 7
VIN = 0 V or VDD
11.4/15.75 200/500 4 500
11.4/15.75 200/500 4 500
11.4/15.75 200/500 4 500
11.4/15.75 200/500 4 500
V min/V max mV min/mV max mA max µA max
Specification Guaranteed Over This Range All Digital Inputs VIL or VIH All Digital Inputs 0 V or VDD
AC PERFORMANCE CHARACTERISTICS
Parameter Output Current Settling Time 1.5
These characteristics are included for Design Guidance only and are not subject to test. (VDD = +11.4 V to +15.75 V, VREF = +10 V, VPIN3 = VPIN4 = O V, VSS = O V or 300 mV, Output Amplifier is AD711 except where noted.)
Units µs max Test Conditions/Comments To 0.003% of Full-Scale Range. IOUT Load= 100 , CEXT = 13 pF. DAC Register Alternately Loaded with All 1s and All 0s. Typical Value of Settling Time Is 0.8 µs. Measured with VREF = 0 V. IOUT Load = 100 , CEXT = 13 pF. DAC Register Alternately Loaded with All 1s and All 0s. VREF = ± 10 V, 10 kHz Sine Wave DAC Register Loaded with All 0s. VDD = ± 5% DAC Register Loaded with All 1s DAC Register Loaded with All 0s Measured Between RFB and IOUT
TA = +25 C TA = TMIN, TMAX
Digital to Analog Glitch Impulse
20
nV-sec typ
Multiplying Feedthrough Error Power Supply Rejection Gain/VDD Output Capacitance COUT (Pin 3) COUT (Pin 3) Output Noise Voltage Density (10 Hz100 kHz)
3 ± 0.01 260 130 15
5 ± 0.02 260 130
mV p-p typ
% per % max pF max pF max nVHz typ
NOTES Temperature range as follows: J, K Versions: 0°C to +70°C A, B Versions: 25°C to +85°C S, T Versions: 55°C to +125°C 2 Specifications are guaranteed for a V DD of +11.4 V to +15.75 V. At V DD = 5 V, the device is fully functional with degraded specifications. 3 Sample tested to ensure compliance. Specifications subject to change without notice.
2
REV. A
AD7538 TIMING CHARACTERISTICS1 All specifications T
Parameter t1 t2 t3 t4 t5 t6 Limit at TA = +25 C 0 0 170 170 140 20 Limit at TA = 0 C to +70 C TA = 25 C to +85 C 0 0 200 200 160 20
(VDD = +11.4 V to +15.75 V, VREF = +10 V, VPIN3 = VPIN4 = 0 V, VSS = 0 V or 300 mV. MIN to TMAX unless otherwise noted. See Figure 1 for Timing Diagram.)
Limit at TA = 55 C to +125 C 0 0 240 240 180 30
Units ns min ns min ns min ns min ns min ns min
Test Conditions/Comments CS to WR Setup Time CS to WR Hold Time LDAC Pulse Width Write Pulse Width Data Setup Time Data Hold Time
NOTES 1 Temperature range as follows: J, K Versions: 0°C to +70°C A, B Versions: 25°C to +85°C S, T Versions: 55°C to +125°C Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(TA= +25°C unless otherwise stated)
VDD (Pin 23) to DGND . . . . . . . . . . . . . . . . . . . 0.3 V, +17 V VSS (Pin 24) to AGND . . . . . . . . . . . . . . . . . . . 15 V, +0.3 V VREF (Pin 1) to AGND . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V VRFB (Pin 2) to AGND . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V Digital Input Voltage (Pins 622) to DGND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, VDD +0.3 V VPIN3 to DGND . . . . . . . . . . . . . . . . . . . . 0.3 V, VDD +0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . 0.3 V, VDD +0.3 V Power Dissipation (Any Package) To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW Derates Above +75°C . . . . . . . . . . . . . . . . . . . . 10 mW/°C
Operating Temperature Range Commercial (J, K Versions) . . . . . . . . . . . . . . 0°C to +70°C Industrial (A, B Versions) . . . . . . . . . . . . . . 25°C to +85°C Extended (S, T Versions) . . . . . . . . . . . . . 55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . 65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7538 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION DIP, SOIC
Figure 1. Timing Diagram
REV. A
3
AD7538
TERMINOLOGY
RELATIVE ACCURACY
in Least Significant Bits. Gain error is adjustable to zero with an external potentiometer.
DIGITAL-TO-ANALOG GLITCH IMPULSE
Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error and is normally expressed in Least Significant Bits or as a percentage of full-scale reading.
DIFFERENTIAL NONLINEARITY
The amount of charge injected from the digital inputs to the analog output when the inputs change state is called Digitalto-Analog Glitch Impulse. This is normally specified as the area of the glitch in either pA-secs or nV-secs depending upon whether the glitch is measured as a current or voltage. It is measured with VREF = AGND.
OUTPUT CAPACITANCE
Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ± 1 LSB max over the operating temperature range ensures monotonicity.
GAIN ERROR
This is the capacitance from IOUT to AGND.
OUTPUT LEAKAGE CURRENT
Gain error is a measure of the output error between an ideal DAC and the actual device output. It is measured with all 1s in the DAC after offset error has been adjusted out and is expressed
Output Leakage Current is current which appears at IOUT with the DAC register loaded to all 0s.
MULTIPLYING FEEDTHROUGH ERROR
This is the ac error due to capacitive feedthrough from VREF terminal to IOUT with DAC register loaded to all zeros.
ORDERING GUIDE
Model AD7538JN AD7538KN AD7538JR AD7538KR AD7538AQ AD7538BQ AD7538SQ AD7538TQ
Temperature Range 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 25°C to +85°C 25°C to +85°C 55°C to +125°C 55°C to +125°C
Relative Accuracy ± 2 LSB ± 1 LSB ± 2 LSB ± 1 LSB ± 2 LSB ± 1 LSB ± 2 LSB ± 1 LSB
Full-Scale Error ± 8 LSB ± 4 LSB ± 8 LSB ± 4 LSB ± 8 LSB ± 4 LSB ± 8 LSB ± 4 LSB
Package Option* N-24 N-24 R-24 R-24 Q-24 Q-24 Q-24 Q-24
*N = Plastic DIP; Q = Cerdip; R = SOIC.
PIN FUNCTION DESCRIPTION
Pin 11 12 13 14 15 619 20 21 22
Mnemonic V REF RF B IOUT AGND DGND DB13DB0 LDAC CS WR
Description Voltage Reference. Feedback Resistor. Used to close the loop around an external op amp. Current Output Terminal. Analog Ground Digital Ground Data Inputs. Bit 13 (MSB) to Bit 0 (LSB). Chip Select Input. Active LOW. Asynchronous Load DAC Input. Active LOW. Write Input. Active LOW. CS 0 1 0 1 X LDAC 1 0 0 1 1 WR 0 X 0 X 1 OPERATION Load Input Register. Load DAC Register from Input Register. Input and DAC Registers are Transparent. No Operation. No Operation.
NOTE: X Don't Care.
23 24
VDD V SS
+12 V to +15 V supply input. Bias pin for High Temperature Low Leakage configuration. To implement low leakage system, the pin should be at a negative voltage. See Figures 4 and 5 for recommended circuitry. 4 REV. A
AD7538
D/A SECTION
Figure 2 shows a simplified circuit diagram for the AD7538 D/A section. The three MSBs of the 14-bit Data Word are decoded to drive the seven switches A-G. The 11 LSBs of the Data Word consist of an R-2R ladder operated in a current steering configuration.
The R-2R ladder current is 1/8 of the total reference input current. 7/8 I flows in the parallel ladder structure. Switches A-G steer equally weighted currents between IOUT and AGND. Since the input resistance at VREF is constant, it may be driven by a voltage source or a current source of positive or negative polarity.
CIRCUIT INFORMATION
Figure 2. Simplified Circuit Diagram for the AD7538 D/A Section
EQUIVALENT CIRCUIT ANALYSIS
Figure 3 shows an equivalent circuit for the analog section of the AD7538 D/A converter. The current source ILEAKAGE is composed of surface and junction leakages. The resistor RO denotes the equivalent output resistance of the DAC which varies with input code. COUT is the capacitance due to the current steering switches and varies from about 90 pF to 180 pF (typical values) depending upon the digital input. g(VREF, N) is the Thevenin equivalent voltage generator due to the reference input voltage, VREF, and the transfer function of the DAC ladder, N.
Figure 4. Unipolar Binary Operation
Table I. Unipolar Binary Code Table for AD7538
Figure 3. AD7538 Equivalent Analog Output Circuit
DIGITAL SECTION
The digital inputs are designed to be both TTL and 5 V CMOS compatible. All logic inputs are static protected MOS gates with typical input currents of less than 1 nA. To minimize power supply currents, it is recommended that the digital input voltages be driven as close as possible to 0 V and 5 V logic levels.
UNIPOLAR BINARY OPERATION (2-QUADRANT MULTIPLICATION)
Binary Number In DAC Register MSB LSB 11 1111 1111 1111
Analog Output, VOUT
16383 V IN 16384 8192 VIN = 1 / 2 V IN 16384
1 VIN 16384
10 0000 0000 0000
Figure 4 shows the circuit diagram for unipolar binary operation. With an ac input, the circuit performs 2 quadrant multiplication. The code table for Figure 4 is given in Table I. Capacitor C1 provides phase compensation and helps prevent overshoot and ringing when high-speed op amps are used.
00 0000 0000 0001 00 0000 0000 0000
0V
REV. A
5
|
|
