|Category||Data Conversion => DAC (Digital to Analog Converters)|
|Datasheet||Download AD7545C datasheet|
FEATURES 12-Bit Resolution Low Gain TC: 2 ppm/C typ Fast TTL Compatible Data Latches Single +15 V Supply Small 20-Lead 0.3" DIP and 20-Terminal Surface Mount Packages Latch Free (Schottky Protection Diode Not Required) Low Cost Ideal for Battery Operated Equipment
The is a monolithic 12-bit CMOS multiplying DAC with onboard data latches. It is loaded by a single 12-bit wide word and directly interfaces to most 12- and 16-bit bus systems. Data is loaded into the input latches under the control of the CS and WR inputs; tying these control inputs low makes the input latches transparent, allowing direct unbuffered operation of the DAC.
The AD7545 is particularly suitable for single supply operation and applications with wide temperature variations. The AD7545 can be used with any supply voltage from +15 V. With CMOS logic levels at the inputs the device dissipates less than 0.5 mW for VDD +5 V.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997
10-Bit Monotonic TMIN to TMAX 12-Bit Monotonic TMIN to TMAX 12-Bit Monotonic TMIN to TMAX 12-Bit Monotonic TMIN to TMAX DAC Register Loaded with 1111 Gain Error Is Adjustable Using the Circuits of Figures 4, 5, and 6 Typical Value is 2 ppm/°C for VDD +5 V VDD 0 V; WR, 0 V
Gain Temperature Coefficient 3 Gain/Temperature DC Supply Rejection 3 Gain/VDD Output Leakage Current at OUT1
Propagation Delay 3 (from Digital Input Change 90% of Final Analog Output) Digital-to-Analog Glitch Inpulse At OUT1 REFERENCE INPUT Input Resistance (Pin 19 to GND) ANALOG OUTPUT Output Capacitance 3 COUT1 DIGITAL INPUTS Input High Voltage VIH Input Low Voltage VIL Input Current6 IIN Input Capacitance3 DB0DB11 WR, CS SWITCHING CHARACTERISTICS 7 Chip Select to Write Setup Time tCS Chip Select to Write Hold Time tCH Write Pulse Width tWR Data Setup Time tDS Data Hold Time tDH POWER SUPPLY IDDTo 1/2 LSB. OUT1 Load = 100. DAC Output Measured from Falling Edge of WR, = 0.
OUT1 Load 100 , CEXT 13 pF4 VREF = AGND VREF V, 10 kHz Sinewave Input Resistance = 300 ppm/°C typ Typical Input Resistance 11 kAll Digital Inputs VIL or VIH All Digital Inputs V to VDD All Digital Inputs V to VDD
NOTES 1 Temperature range as follows: L, GL versions, C, GC versions, U GU versions, +125°C. 2 This includes the effect of 5 ppm max gain TC. 3 Guaranteed but not tested. V to VDD or VDD V. 5 Feedthrough can be further reduced by connecting the metal lid on the ceramic package (Suffix D) to DGND. 6 Logic inputs are MOS gates. Typical input current (+25°C) is less than 1 nA. 7 Sample tested +25°C to ensure compliance. Specifications subject to change without notice.
MODE SELECTION HOLD MODE: EITHER OR WR HIGH, DATA BUS (DB0DB11) IS LOCKED OUT; DAC HOLDS LAST DATA PRESENT WHEN OR CS ASSUMED HIGH STATE.
NOTES: VDD = 20ns VDD = 40ns ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 90% OF VDD. TIMING MEASUREMENT REFERENCE LEVEL IS VIH + VIL/2.
VDD to DGND. +17 V Digital Input Voltage to DGND. 0.3 V, VDD +0.3 V VRFB, VREF to DGND. VPIN1 to DGND. 0.3 V, VDD +0.3 V AGND to DGND. 0.3 V, VDD 0.3 V Power Dissipation (Any Package) 450 mW Derates above +75°C. 6 mW/°C Operating Temperature
Commercial (J, K, L, GL) Grades. to +70°C Industrial (A, B, C, GC) Grades. to +85°C Extended (S, T, U, GU) Grades. to +125°C Storage Temperature. to +150°C Lead Temperature (Soldering, 10 secs). +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7545 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
The amount by which the D/A converter transfer function differs from the ideal transfer function after the zero and fullscale points have been adjusted. This is an endpoint linearity measurement.
The difference between the measured change and the ideal change between any two adjacent codes. If a device has a differential nonlinearity of less than 1 LSB it will be monotonic, i.e., the output will always increase for an increase in digital code applied to the D/A converter.
This is a measure of the internal delay of the circuit and is measured from the time a digital input changes to the point at which the analog output at OUT1 reaches 90% of its final value.
This is a measure of the amount of charge injected from the digital inputs to the analog outputs when the inputs change state. It is usually specified as the area of the glitch in nV secs and is measured with VREF = AGND and ADLH0032CG as the output op amp, C1 (phase compensation) = 33 pF.
NOTES 1 Analog Devices reserves the right to ship either ceramic (D-20) in lieu of cerdip packages 2 To order MIL-STD-883, Class B process parts, add /883B to part number. Contact local sales office for military data sheet. For U.S. Standard Military DRAWING (SMD) see DESC drawing E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip.
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