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Details, datasheet, quote on part number:AD7677ASTRL
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| Part: | AD7677ASTRL |
| Category: | Data Conversion => ADC (Analog to Digital Converters) |
| Description: | 16-Bit, 1 LSB Inl, 1 MSPS Differential Pulsar ADC.<<<>>>the AD7677 is a 16-bit, 1 Msps, 1 LSB Inl, Charge Redistribution Sar, Fully Differential Analog-to-digital Converter That Operates From a Single 5 V Power Supply. The AD7677 is The Flagship Part of The New Pulsar Family - Simultaneously Being The Fastest as Well as The Industry's MOSt Accurate 16-bit Sar ADC Ever Introduced . The Part Contains a High-speed 16-bit Sampling ADC, an Internal Conversion Clock, Error Correction Circuits, And Both Serial And Parallel System Interface Ports.<<<>>>features <<<>>> <<<>>><<<>>>Throughput: 1 MSPS <<<>>>INL: 1 LSB Max ( 0.0015% of Full Scale) <<<>>>16 Bits Resolution With no Missing Codes <<<>>>S/(N+D): 94 DB TYP @ 45 KHZ <<<>>>THD: 110 DB TYP @ 45 KHZ <<<>>>Differential Input Range: 2.5 V <<<>>>Both ac And DC Specifications <<<>>>No Pipeline Delay <<<>>>Parallel (8 Bits/16 Bits) And Serial 5 V/3 V Interface <<<>>>Single 5 V Supply Operation <<<>>>115 MW Typical Power Dissipation, 15 µW @ 100 SPS <<<>>>Power-Down Mode: 7 µW Max |
| Company: | Analog Devices |
| Datasheet: | Download AD7677ASTRL datasheet File size : 1266 kB |
| Request For quote: | Find where to buy AD7677ASTRL
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Datasheet text preview:
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FEATURES Throughput: 1 MSPS INL: 1 LSB Max ( 0.0015% of Full Scale) 16 Bits Resolution with No Missing Codes S/(N+D): 94 dB Typ @ 45 kHz THD: 110 dB Typ @ 45 kHz Differential Input Range: 2.5 V Both AC and DC Specifications No Pipeline Delay Parallel (8 Bits/16 Bits) and Serial 5 V/3 V Interface Single 5 V Supply Operation 115 mW Typical Power Dissipation, 15 W @ 100 SPS Power-Down Mode: 7 W Max Packages: 48-Lead Quad Flatpack (LQFP) 48-Lead Frame Chip Scale (LFCSP) Pin-to-Pin Compatible Upgrade of the AD7664/AD7675/ AD7676 APPLICATIONS CT Scanners Data Acquisition Instrumentation Spectrum Analysis Medical Instruments Battery-Powered Systems Process Control
16-Bit, 1 LSB INL, 1 MSPS Differential ADC AD7677*
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND REF REFGND DVDD DGND OVDD
AD7677
IN+ IN SERIAL PORT SWITCHED CAP DAC 16
OGND
SER/PAR BUSY DATA[15:0] CLOCK
PD RESET
PARALLEL INTERFACE
CS RD OB/2C BYTESWAP
CONTROL LOGIC AND CALIBRATION CIRCUITRY
WARP
IMPULSE
CNVST
PulSAR Selection
Type/kSPS Pseudo Differential True Bipolar True Differential
100250 AD7660 AD7663 AD7675
500570 AD7650 AD7664 AD7665 AD7676
1000
AD7671 AD7677
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7677 is a 16-bit, 1 MSPS, charge redistribution SAR, fully differential, analog-to-digital converter that operates from a single 5 V power supply. The part contains a high speed 16-bit sampling ADC, an internal conversion clock, error correction circuits, and both serial and parallel system interface ports. The AD7677 is hardware factory calibrated and comprehensively tested to ensure such ac parameters as signal-to-noise ratio (SNR) and total harmonic distortion (THD), in addition to the more traditional dc parameters of gain, offset, and linearity. It features a very high sampling rate mode (Warp); a fast mode (Normal) for asynchronous conversion rate applications; and, for low power applications, a reduced power mode (Impulse) where the power is scaled with the throughput. The AD7677 is available in a 48-lead LQFP or a tiny 48-lead LFCSP with operation specified from 40°C to +85°C.
1. Excellent INL The AD7677 has a maximum integral nonlinearity of 1 LSB with a no missing 16-bit code. 2. Superior AC Performances The AD7677 has a minimum dynamic of 92 dB, 94 dB typical. 3. Fast Throughput The AD7677 is a 1 MSPS, charge redistribution, 16-bit SAR ADC with internal error correction circuitry. 4. Single-Supply Operation The AD7677 operates from a single 5 V supply and typically dissipates only 115 mW. Its power dissipation decreases with the throughput. It consumes 7 µW maximum when in power-down. 5. Serial or Parallel Interface Versatile parallel (8 bits or 16 bits) or 2-wire serial interface arrangement compatible with both 3 V or 5 V logic.
*Patent pending
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002
AD7677SPECIFICATIONS (40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise stated.)
Parameter Conditions Min Typ Max Unit
RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Analog Input CMRR Input Current Input Impedance THROUGHPUT SPEED Complete Cycle Throughput Rate Time Between Conversions Complete Cycle Throughput Rate Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error Differential Linearity Error No Missing Codes Transition Noise +Full-Scale Error3 Full Scale Error3 Zero Error3 +Full-Scale Error3 Full Scale Error3 Zero Error3 Power Supply Sensitivity AC ACCURACY Signal-to-Noise Spurious Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise+Distortion) 3 dB Input Bandwidth SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response REFERENCE External Reference Voltage Range External Reference Current Drain DIGITAL INPUTS Logic Levels V IL V IH I IL I IH DIGITAL OUTPUTS Data Format Pipeline Delay V OL V OH ISINK = 1.6 mA ISOURCE = 100 µA V I N + VI N VIN+, VIN to AGND fIN = 10 kHz 1 MSPS Throughput
16 V REF 0.1 85 11 See Analog Input Section 1 1 1 1.25 800 1.5 666 +1 +1 0.35 In Warp Mode In Warp Mode In Warp Mode In Impulse or Normal Mode In Impulse or Normal Mode In Impulse or Normal Mode AVDD = 5 V ± 5% fIN = 20 kHz fIN = 45 kHz fIN = 20 kHz fIN = 45 kHz fIN = 20 kHz fIN = 45 kHz fIN = 20 kHz fIN = 45 kHz fIN = 45 kHz, 60 dB Input 25 20 15 40 20 23 +25 +20 +15 +40 +20 +23 + VREF +3
Bits V V dB µA µs MSPS ms µs kSPS µs kSPS LSB1, 2 LSB2 Bits LSB LSB LSB LSB LSB LSB LSB LSB d B2 , 4 dB dB2 dB dB2 dB dB2 dB MHz ns ps rms ns V µA
In Warp Mode In Warp Mode In Warp Mode In Normal Mode In Normal Mode In Impulse Mode In Impulse Mode
0.001 0 0 1 1 16
± 1.4 94 94 110 110 110 110 94 94 34 15.8 2 5
92 104.5
103.5
92
Full-Scale Step 2.3 1 MSPS Throughput 2.5 37
250 AVDD 1.85
0.3 2.0 1 1
+0.8 DVDD + 0.3 +1 +1
V V µA µA
Parallel or Serial 16-Bit Conversion Results Available Immediately after Completed Conversion 0.4 OVDD 0.6
V V
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Parameter Conditions Min Typ Max Unit
POWER SUPPLIES Specified Performance AVDD DVDD OVDD Operating Current2 AVDD D V D D6 O V D D6 Power Dissipation6 In Power-Down Mode8 TEMPERATURE RANGE9 Specified Performance
4.75 4.75 2.7 1 MSPS Throughput
5 5
5.25 5.25 5 . 2 55
V V V mA mA µA mW µW mW µW °C
666 kSPS Throughput7 100 SPS Throughput7 1 MSPS Throughput2
16.7 6.4 69 87 15 115
98 130 7 +85
TMIN to TMAX
40
NOTES 1 LSB means Least Significant Bit. With the ± 2.5 V input range, one LSB is 76.3 µV. 2 In Warp Mode. 3 Tested with V REF = 2.5 V. See Definition of Specifications section. These specifications do not include the error contribution from the external reference. 4 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale unless otherwise specified. 5 The max should be the minimum of 5.25 V and DVDD + 0.3 V. 6 Tested in Parallel Reading Mode. 7 In Impulse Mode. 8 With OVDD below DVDD + 0.3 V and all digital inputs forced to DVDD or DGND, respectively. 9 Contact factory for extended temperature range. Specifications subject to change without notice.
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AD7677 TIMING SPECIFICATIONS (40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise stated.)
Symbol Refer to Figures 11 and 12 Convert Pulsewidth Time Between Conversions (Warp Mode/Normal Mode/Impulse Mode) CNVST LOW to BUSY HIGH Delay BUSY HIGH All Modes Except in Master Serial Read after Convert Mode (Warp Mode/Normal Mode/Impulse Mode) Aperture Delay End of Conversion to BUSY LOW Delay Conversion Time (Warp Mode/Normal Mode/Impulse Mode) Acquisition Time RESET Pulsewidth Refer to Figures 13, 14, and 15 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay (Warp Mode/Normal Mode/Impulse Mode) DATA Valid to BUSY LOW Delay Bus Access Request to DATA Valid Bus Relinquish Time Refer to Figures 17 and 18 (Master Serial Interface Modes) CS LOW to SYNC Valid Delay CS LOW to Internal SCLK Valid Delay CS LOW to SDOUT Delay CNVST LOW to SYNC Delay (Read During Convert) (Warp Mode/Normal Mode/Impulse Mode) SYNC Asserted to SCLK First Edge Delay3 Internal SCLK Period3 Internal SCLK HIGH3 Internal SCLK LOW3 SDOUT Valid Setup Time3 SDOUT Valid Hold Time3 SCLK Last Edge to SYNC Delay3 CS HIGH to SYNC HI-Z CS HIGH to Internal SCLK HI-Z CS HIGH to SDOUT HI-Z BUSY HIGH in Master Serial Read After Convert3 CNVST LOW to SYNC Asserted Delay (Warp Mode/Normal Mode/Impulse Mode) SYNC Deasserted to BUSY LOW Delay Refer to Figures 19 and 20 (Slave Serial Interface Modes) External SCLK Setup Time External SCLK Active Edge to SDOUT Delay SDIN Setup Time SDIN Hold Time External SCLK Period External SCLK HIGH External SCLK LOW
2
Min 5 1/1.25/1.5
Typ
Max
Unit ns µs ns µs ns ns µs ns ns
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t1 1 t12 t13 t14 t1 5 t16 t1 7 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t3 0 t31 t3 2 t33 t34 t35 t36 t37
Note 1 30 0.75/1/1.25
2 10 0.75/1/1.25 250 10 0.75/1/1.25 45 5 40 15 10 10 10 25/275/525 3 25 12 7 4 2 3
µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns ns ns ns ns ns ns ns
40
10 10 10 See Table I 0.75/1/1.25 25 5 3 5 5 25 10 10
18
NOTES 1 In Warp Mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time. 2 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C L of 10 pF; otherwise, the load is 60 pF maximum. 3 In serial master read during convert mode. See Table I for serial master read after convert mode. Specifications subject to change without notice.
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Table I. Serial Clock Timings in Master Read after Convert
DIVSCLK[1] DIVSCLK[0] SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum Internal SCLK Period Maximum Internal SCLK HIGH Minimum Internal SCLK LOW Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum SCLK Last Edge to SYNC Delay Minimum Busy High Width Maximum (Warp) Busy High Width Maximum (Normal) Busy High Width Maximum (Impulse)
ABSOLUTE MAXIMUM RATINGS 1
0 0 t1 8 t1 9 t19 t20 t21 t2 2 t2 3 t2 4 t2 4 t2 4 t2 4 3 25 40 12 7 4 2 3 1.5 1.75 2
0 1 17 50 70 22 21 18 4 60 2 2.25 2.5
1 0 17 100 140 50 49 18 30 140 3 3.25 3.5
1 1 17 200 280 100 99 18 89 300 5.25 5.55 5.75
Unit ns ns ns ns ns ns ns ns µs µs µs
Analog Inputs IN+2, IN2, REF, REFGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVDD + 0.3 V to AGND 0.3 V Ground Voltage Differences AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . ± 0.3 V Supply Voltages AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . 0.3 V to +7 V AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . . ± 7 V DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V Digital Inputs . . . . . . . . . . . . . . . . . 0.3 V to DVDD + 0.3 V Internal Power Dissipation3 . . . . . . . . . . . . . . . . . . . . 700 mW Internal Power Dissipation4 . . . . . . . . . . . . . . . . . . . . . . 2.5 W Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Storage Temperature Range . . . . . . . . . . . . 65°C to +150°C Lead Temperature Range ( S o l d e r i n g 1 0 s e c ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 0° C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 See Analog Input section. 3 Specification is for device in free air: 48-Lead LQFP: JA = 91°C/W, JC = 30°C/W. 4 Specification is for device in free air: LFCSP: JA = 26°C/W
1.6mA
IOL
TO OUTPUT PIN
CL 60pF1 500 A
1.4V
IOH
NOTE 1 IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Figure 1. Load Circuit for Digital Interface Timing, SDOUT, SYNC, SCLK Outputs, CL = 10 pF
2V 0.8V
tDELAY
2V 0.8V
tDELAY
2V 0.8V
Figure 2. Voltage Reference Levels for Timings
ORDERING GUIDE
Model AD7677AST AD7677ASTRL AD7677ACP AD7677ACPRL EVAL-AD7677CB1 EVAL-CONTROL BRD22
Temperature Range 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C
Package Description Quad Flatpack (LQFP) Quad Flatpack (LQFP) Chip Scale (LFCSP) Chip Scale (LFCSP) Evaluation Board Controller Board
Package Option ST-48 ST-48 CP-48 CP-48
NOTES 1 This board can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/ demonstration purposes. 2 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7677 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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