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Details, datasheet, quote on part number:AD7679
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Datasheet text preview:
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PRELIMINARY TECHNICAL DATA
18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC Preliminary Technical Data AD7679
F U N C T I O N A L BLOCK DIAGRAM
PDBUF AGND AVDD REFBUFIN IN+ INSWITCHED CAP DAC PARALLEL INTERFACE CLOCK PD RESET CONTROL LOGIC AND CALIBRATION CIRCUITRY REF REFGND DVDD DGND OVDD SERIAL PORT 18 D[17:0] BUSY RD CS MODE0 MODE1 OGND
FEATURES 18 Bits Resolution with No Missing Codes No Pipeline Delay ( SAR architecture ) Differential Input Range: VREF (VREF up to 5V) Throughput: 570 kSPS INL: 2.5 LSB Max ( 9.5 ppm of Full-Scale) Dynamic Range : 103 dB Typ ( VREF = 5V ) S/(N+D): 100 dB Typ @ 2 kHz ( VREF = 5V ) THD: 115 dB Typ @ 2 kHz Parallel (18,16 or 8bits bus) and Serial 5V/3V Interface SPI/QSPI/MICROWIRE/DSP Compatible On-board Reference Buffer Single 5 V Supply Operation Power Dissipation: 68 mW @ 500 kSPS 136 W @ 1 kSPS Power-Down Mode: 7 W Max Package: 48-Lead Quad Flat Pack (LQFP) 48-Lead Frame Chip Scale Package (LFCSP) Pin-to-Pin Compatible with the AD7676/AD7678/AD7674 APPLICATIONS CT Scanners High Dynamic Data Acquisition Geophone and hydrophone sensor Sigma-Delta replacement (low power, multichannel) Instrumentation Spectrum Analysis Medical Instruments
AD7679
CNVST
PulSAR Selection
Type / kSPS Pseudo Differential True Bipolar True Differential 18 Bit Multichannel/ Simultaneous
100 - 250 AD7651 AD7660/61 AD7663 AD7675 AD7678
500 - 100 800 - 1000 AD7650/52 AD7653 AD7664/66 AD7667 AD7665 AD7676 AD7679 AD7654 AD7655 AD7671 AD7677 AD7674
G E N E R A L DESCRIPTION
P R O D U C T HIGHLIGHTS
The AD7679 is a 18-bit, 570 kSPS, charge redistribution SAR, fully differential analog-to-digital converter that operates from a single 5 V power supply. The part contains a high-speed 18-bit sampling ADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports. The AD7679 is hardware factory calibrated and is comprehensively tested to ensure such ac parameters as signal-to-noise ratio (SNR) and total harmonic distortion (THD), in addition to the more traditional dc parameters of gain, offset, and linearity. It is fabricated using Analog Devices' high-performance, 0.6 micron CMOS process and is available in a 48-lead LQFP or a 48-lead LFCSP with operation specified from 40°C to +85°C. REV. PrC
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
1 . High resolution and Fast Throughput The AD7679 is a 570 kSPS, charge redistribution, 18-bit SAR ADC ( no latency ). 2 . E x c e l l e n t accuracy The AD7679 has a maximum integral nonlinearity of 2.5 LSB with no missing 18-bit code. 3 . S i n g l e - S u p p l y Operation The AD7679 operates from a single 5 V supply and can typically dissipate only 68 m W at 500kSPS. Its power dissi pation decreases with the throughput to, for instance, 136 W at 1kSPS. It consumes 7 W maximum when in power-down. 5 . Serial or Parallel Interface Versatile parallel (18, 16 or 8 bits bus) or 2-wire serial interface arrangement compatible with both 3 V or 5 V logic.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2003
PRELIMINARY TECHNICAL DATA
AD7679SPECIFICATIONS
Parameter RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Analog Input CMRR Input Current Input Impedance THROUGHPUT SPEED C o m p l e t e Cycle T h r o u g h p u t Rate D C ACCURACY I n t e g r a l Linearity Error D i f f e r e n t i a l Linearity Error N o Missing Codes T r a n s i t i o n Noise G a i n Error, T M I N to T M A X2 G a i n Error Temperature Drift Zero Error, T M I N to T MAX 2 Z e r o Error Temperature Drift P o w e r Supply Sensitivity A C ACCURACY Signal-to-Noise
(40 C to +85 C, VREF = 4.096V, AVDD = DVDD= 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.) )
Min 18 Typ Max Unit Bits +VREF AVDD TBD TBD See Analog Input Section 1.75 570 +2.5 +1.5 0.7 ±TBD ±TBD ±TBD ±TBD ±TBD 101 99 TBD TBD 103 115 TBD TBD 115 TBD TBD 100 40 TBD 2 TBD ±TBD V V dB µA
Conditions
VI N + V I N VIN+, VIN- to AGND fIN = TBD kHz TBD kSPS Throughput
-VREF 0.1
0 2.5 1 18 V REF= 5 V
µs kSPS LSB1 LSB Bits LSB % of FSR ppm/°C LSB ppm/°C LSB dB3 dB dB dB dB dB dB dB dB dB dB dB dB MHz ns ps rms ns ns V V V µA µA
A V D D = 5 V ± 5% f IN = 2 kHz, V R E F= 5 V VREF=4.096V 9 8 f IN = 10 kHz f IN = 100 kHz V IN+= V IN-= V REF/ 2 = 2 . 5 V 1 0 1 fIN = 2 kHz f IN = 10 kHz f IN = 100 kHz fIN = 2 kHz f IN = 10 kHz f IN = 100 kHz fIN = 2 kHz, fIN = 2 kHz,60 dB Input
D y n a m i c range S p u r i o u s Free Dynamic Range T o t a l Harmonic Distortion Signal-to-(Noise+Distortion) 3 dB Input Bandwidth SAMPLING DYNAMICS Aperture Delay Aperture Jitter T r a n s i e n t Response O v e r v o l t a g e recovery REFERENCE External Reference Voltage Range REF Voltage with reference buffer Reference Buffer Input Voltage Range REFBUFIN Input Current R E F Current Drain DIGITAL Logic Levels VI L VIH IIL IIH INPUTS
F u l l - S c a l e Step
250 250 2.5 4.05 1.5 1 4.096 4.096 2.5 TBD AVDD 4.15 TBD +1
REF REFBUFIN = 2.5V REFBUFIN 5 7 0 kSPS Throughput
0.3 +2.0 1 1
+0.8 DVDD + 0.3 +1 +1
V V µA µA
DIGITAL OUTPUTS Data Format Pipeline Delay VO L VO H ISINK = 1.6 mA ISOURCE = 500 µA
Parallel or Serial 18-Bits Conversion Results Available Immediately After Completed Conversion 0.4 OVDD 0.6
V V
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REV. PrC
PRELIMINARY TECHNICAL DATA AD7679
Parameter POWER SUPPLIES S p e c i f i e d Performance AVDD DVDD OVDD O p e r a t i n g Current AVDD DVDD5 OVDD5 Power Dissipation5 Conditions Min Typ Max Unit
4.75 4.75 2.7 5 0 0 kSPS Throughput
5 5 9.6 3.9 60 73 83 68 136
5.25 V 5.25 V DVDD+0.34 V mA mA µA mW mW mW µW µW °C
PDBUF low @500 kSPS PDBUF low @570 kSPS PDBUF high @500 kSPS PDBUF high @1 kSPS In Power-Down Mode6 TMIN to TMAX 40
TBD TBD 7 +85
TEMPERATURE RANGE7 Specified Performance
NOTES 1 L S B means Least Significant Bit. With the ±4.096 V input range, one LSB is 31.25 µV. 2 S e e Definition of Specifications section. These specifications do not include the error contribution from the external reference. 3 A l l specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified. 4 T h e max should be the minimum of 5.25V and DVDD+0.3V. 5 T e s t e d in parallel reading mode. 6 W i t h all digital inputs forced to DVDD or DGND respectively. 7 C o n t a c t factory for extended temperature range. S p e c i f i c a t i o n s subject to change without notice.
TIMING SPECIFICATIONS
(40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Symbol Min 5 1.75 30 1.5 2 10 1.5 250 10 1.5 45 5 40 15 Typ Max Unit ns µs ns µs ns ns µs ns ns µs ns ns ns
REFER TO FIGURES 12 AND 13 C o n v e r t Pulsewidth T i m e Between Conversions CNVST LOW to BUSY HIGH Delay BUSY HIGH All Modes Except in Master Serial Read After Convert A p e r t u r e Delay End of Conversion to BUSY LOW Delay C o n v e r s i o n Time A c q u i s i t i o n Time R E S E T Pulsewidth REFER TO FIGURES 14, 15, AND 16 (Parallel Interface Modes) CNVST LOW to Data Valid Delay Data Valid to BUSY LOW Delay Bus Access Request to Data Valid Bus Relinquish Time
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13
REV. PrC
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PRELIMINARY TECHNICAL DATA AD7679 TIMING SPECIFICATIONS (continued)
Symbol REFER TO FIGURES 18 AND 19 (Master Serial Interface Modes)1 CS LOW to SYNC Valid Delay CS LOW to Internal SCLK Valid Delay CS LOW to SDOUT Delay CNVST LOW to SYNC Delay SYNC Asserted to SCLK First Edge Delay2 Internal SCLK Period2 Internal SCLK HIGH2 Internal SCLK LOW 2 SDOUT Valid Setup Time2 SDOUT Valid Hold Time2 SCLK Last Edge to SYNC Delay2 CS HIGH to SYNC HI-Z CS HIGH to Internal SCLK HI-Z CS HIGH to SDOUT HI-Z BUSY HIGH in Master Serial Read after Convert2 CNVST LOW to SYNC Asserted Delay SYNC Deasserted to BUSY LOW Delay REFER TO FIGURES 20 AND 22 (Slave Serial Interface Modes) E x t e r n a l SCLK Setup Time External SCLK Active Edge to SDOUT Delay S D I N Setup Time SDIN Hold Time E x t e r n a l SCLK Period E x t e r n a l SCLK HIGH E x t e r n a l SCLK LOW Min Typ Max Unit t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 t36 t37 10 10 10 525 3 25 12 7 4 2 3 40 ns ns ns ns ns ns ns ns ns ns ns ns ns µs µs ns ns ns ns ns ns ns ns
10 10 10 See Table I 1.5 25 5 3 5 5 25 10 10
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NOTES 1 I n serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C L of 10 pF; otherwise, the load is 60 pF maximum. 2 I n serial master read during convert mode. See Table I for serial master read after convert mode. S p e c i f i c a t i o n s subject to change without notice.
Table I. Serial clock timings in Master Read after Convert DIVSCLK[1] DIVSCLK[0] S Y N C to SCLK First Edge Delay Minimum I n t e r n a l SCLK Period minimum I n t e r n a l SCLK Period Maximum I n t e r n a l SCLK HIGH Minimum I n t e r n a l SCLK LOW Minimum S D O U T Valid Setup Time Minimum S D O U T Valid Hold Time Minimum S C L K Last Edge to SYNC Delay Minimum B u s y High Width Maximum 0 0 3 25 40 12 7 4 2 3 2.25 0 1 17 50 70 22 21 18 4 60 2.75 1 0 17 100 140 50 49 18 30 140 3.75 1 1 17 200 280 100 99 18 89 300 6 unit ns ns ns ns ns ns ns ns µs
t18 t19 t19 t20 t21 t22 t23 t24 t28
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REV. PrC
PRELIMINARY TECHNICAL DATA AD7679
A B S O L U T E MAXIMUM RATINGS1
Analog Inputs I N +2, IN-2, REF, REFBUFIN, REFGND to AGND . . . . . . . . . . . . . . . . . AVDD + 0.3 V to AGND 0.3 V G r o u n d Voltage Differences A G N D , DGND, OGND . . . . . . . . . . . . . . . . . . . ±0.3 V S u p p l y Voltages AVDD, DVDD, OVDD . . . . . . . . . . . . . -0.3V to +7 V AVDD to DVDD, AVDD to OVDD . . . . . . . . . ±7 V DVDD to OVDD . . . . . . . . . . . . . . . . . . -0.3V to +7 V Digital Inputs . . . . . . . . . . . . 0.3 V to DVDD + 0.3V I n t e r n a l Power Dissipation 3 . . . . . . . . . . . . . . . . 700 mW I n t e r n a l Power Dissipation 4 . . . . . . . . . . . . . . . . . . . 2 . 5 W J u n c t i o n Temperature . . . . . . . . . . . . . . . . . . . . . . . . 1 5 0 ° C Storage Temperature Range . . . . . . . . . 65°C to +150°C Lead Temperature Range ( S o l d e r i n g 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 0 ° C
NOTES 1 S t r e s s e s above those listed under Absolute Maximum Ratings may c a u s e permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above t h o s e indicated in the operational section of this specification is not i m p l i e d . Exposure to absolute maximum rating conditions for ext e n d e d periods may affect device reliability. 2 S e e Analog Input section. 3 Specification is for device in free air: 48-Lead LQFP: JA = 91°C/W, JC = 30°C/W. 4 Specification is for device in free air: 48-Lead LFCSP: JA = 26°C/W.
1.6mA
IOL
TO OUTPUT PIN
1.4V CL 60pF* 500 A IOH
*IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Figure 1. Load Circuit for Digital Interface Timing, SD OUT, SYNC, SCLK Outputs, CL = 10 pF
2V 0.8V
tDELAY
2V 0.8V
tDELAY
2V 0.8V
Figure 2. Voltage Reference Levels for Timing
O R D E R I N G GUIDE
Model AD7679AST AD7679ASTRL AD7679ACP AD7679ACPRL EVAL-AD7679CB1 E V A L - C O N T R O L BRD2 2
Temperature Range 40°C 40°C 40°C 40°C to to to to +85°C +85°C +85°C +85°C
Package Description Q u a d Flatpack (LQFP) Q u a d Flatpack (LQFP) C h i p Scale (LFCSP) C h i p Scale (LFCSP) E v a l u a t i o n Board C o n t r o l l e r Board
Package Option ST-48 ST-48 CP-48 CP-48
NOTES 1 T h i s board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes. 2 T h i s board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although t h e AD7679 features proprietary ESD protection circuitry, permanent damage may o c c u r on devices subjected to high-energy electrostatic discharges. Therefore, proper E S D precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. PrC
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