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Details, datasheet, quote on part number:AD768-EB
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Datasheet text preview:
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FEATURES 30 MSPS Update Rate 16-Bit Resolution Linearity: 1/2 LSB DNL @ 14 Bits 1 LSB INL @ 14 Bits Fast Settling: 25 ns Full-Scale Settling to 0.025% SFDR @ 1 MHz Output: 86 dBc THD @ 1 MHz Output: 71 dBc Low Glitch Impulse: 35 pV-s Power Dissipation: 465 mW On-Chip 2.5 V Reference Edge-Triggered Latches Multiplying Reference Capability APPLICATIONS Arbitrary Waveform Generation Communications Waveform Reconstruction Vector Stroke Display PRODUCT DESCRIPTION
DCOM (MSB) DB15
16-Bit, 30 MSPS D/A Converter AD768
FUNCTIONAL BLOCK DIAGRAM
VDD
AD768
MSBs: SEGMENTED CURRENT SOURCES AND SWITCHES MSB DECODER AND EDGETRIGGERED BIT LATCHES
LSBs: CURRENT SOURCES, SWITCHES, AND 1k R-2R LADDERS
IOUTA IOUTB 1k 1k LADCOM
DB0 (LSB) CLOCK NC
2.5V BANDGAP REFERENCE
CONTROL AMP
VEE
REFCOM REFOUT
IREFIN
NR
The AD768 is a 16-bit, high speed digital-to-analog converter (DAC) that offers exceptional ac and dc performance. The AD768 is manufactured on ADI's Advanced Bipolar CMOS (ABCMOS) process, combining the speed of bipolar transistors, the accuracy of laser-trimmable thin film resistors, and the efficiency of CMOS logic. A segmented current source architecture is combined with a proprietary switching technique to reduce glitch energy and maximize dynamic accuracy. Edge triggered input latches and a temperature compensated bandgap reference have been integrated to provide a complete monolithic DAC solution. The AD768 is a current-output DAC with a nominal full-scale output current of 20 mA and a 1 k output impedance. Differential current outputs are provided to support single-ended or differential applications. The current outputs may be tied directly to an output resistor to provide a voltage output, or fed to the summing junction of a high speed amplifier to provide a buffered voltage output. Also, the differential outputs may be interfaced to a transformer or differential amplifier. The on-chip reference and control amplifier are configured for maximum accuracy and flexibility. The AD768 can be driven by the on-chip reference or by a variety of external reference voltages based on the selection of an external resistor. An external capacitor allows the user to optimally trade off reference bandwidth and noise performance. The AD768 operates on ± 5 V supplies, typically consuming 465 mW of power. The AD768 is available in a 28-pin SOIC package and is specified for operation over the industrial temperature range. REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
PRODUCT HIGHLIGHTS
1. The low glitch and fast settling time provide outstanding dynamic performance for waveform reconstruction or digital synthesis requirements, including communications. 2. The excellent dc accuracy of the AD768 makes it suitable for high speed A/D conversion applications. 3. On-chip, edge-triggered input CMOS latches interface readily to CMOS logic families. The AD768 can support update rates up to 40 MSPS. 4. A temperature compensated, 2.5 V bandgap reference is included on-chip allowing for generation of the reference input current with the use of a single external resistor. An external reference may also be used. 5. The current output(s) of the AD768 may be used singly or differentially, either into a load resistor, external op amp summing junction or transformer. 6. Proper selection of an external resistor and compensation capacitor allow the performance-conscious user to optimize the AD768 reference level and bandwidth for the target application.
© Analog Devices, Inc., 1996 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD768SPECIFICATIONS
Parameter RESOLUTION DC ACCURACY Linearity Error TA = +25°C TMIN to TMAX Differential Nonlinearity TA = +25°C TMIN to TMAX Monotonicity (13-Bit) ANALOG OUTPUT Offset Error Gain Error Full-Scale Output Current2 Output Compliance Range Output Resistance Output Capacitance REFERENCE OUTPUT Reference Voltage Reference Output Current3 REFERENCE INPUT Reference Input Current Reference Bandwidth4 Small Signal, IREF = 5 mA ± 0.1 mA Large Signal, IREF = 4 mA ± 2 mA TEMPERATURE COEFFICIENTS Unipolar Offset Drift Gain Drift5 Gain Drift6 Reference Voltage Drift DYNAMIC PERFORMANCE7 Maximum Output Update Rate Output Settling Time (tST) (to 0.025%) Output Propagation Delay (tPD) Glitch Impulse Output Rise Time (10% to 90%) Output Fall Time (10% to 90%) Output Noise (DB0DB15 High, into 50 ) Differential Gain Error Differential Phase Error DIGITAL INPUTS Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Input Capacitance Input Setup Time (tS) Input Hold Time (tH) Latch Pulse Width (tLPW)
1
(TMIN to TMAX , VDD = +5.0 V, VEE = 5.0 V, LADCOM, REFCOM, DCOM = 0 V, IREFIN = 5 mA, CLOCK = 10 MHz, unless otherwise noted)
Min 16 Typ Max Units Bits
8 8
±4
+8 +8
LSB LSB
6 ±2 +6 LSB 8 +8 LSB GUARANTEED OVER RATED SPECIFICATION TEMPERATURE RANGE 0.2 1.0 20 1.2 0.8 1.0 3 2.5 +5.0 5 28 9 5 20 40 30 30 40 25 10 35 5 5 3 0.01 0.01 +5 +20 +40 +30 +5.0 1.2 +0.2 +1.0 % of FSR % of FSR mA V k pF V mA mA MHz MHz ppm of FSR/oC ppm of FSR/oC ppm of FSR/oC ppm/oC MSPS ns ns pV-s ns ns nV/ Hz % Degree V V µA µA pF ns ns ns
2.475
2.525 +15 7
1
35
3.5 10 10 10 10 5 10 1.5 +10 +10
AC LINEARITY7 Spurious-Free Dynamic Range (SFDR Within a Window) FOUT = 1.002 MHz; CLOCK = 10 MHz; 2 MHz Span FOUT = 1.002 MHz; CLOCK = 20 MHz; 2 MHz Span FOUT = 5.002 MHz; CLOCK = 30 MHz; 10 MHz Span Spurious-Free Dynamic Range (SFDR to Nyquist) FOUT = 1.002 MHz; CLOCK = 10 MHz FOUT = 1.002 MHz; CLOCK = 20 MHz FOUT = 5.002 MHz; CLOCK = 30 MHz Total Harmonic Distortion (THD) FOUT = 1.002 MHz; CLOCK = 10 MHz FOUT = 1.002 MHz; CLOCK = 20 MHz FOUT = 5.002 MHz; CLOCK = 30 MHz 2
86 85 78 74 73 67 71 66 61
79
dB dB dB dB dB dB dB dB dB REV. B
70
68
AD768
Parameter POWER SUPPLY Positive Voltage Range Negative Voltage Range Positive Supply Current Negative Supply Current Nominal Power Dissipation Power Supply Rejection Ratio (PSRR) OPERATING RANGE Min 4.75 5.25 Typ 5 5 30 63 465 Max 5.25 4.75 40 73 600 +0.2 +85 Units V V mA mA mW % of FSR/V °C
0.2 40
NOTES 1 Measured at IOUTA, driving a virtual ground. 2 Nominal FS output current is 4× the current at IREFIN. Therefore, nominal FS current is 20 mA when IREFIN = 5 mA. 3 Output current is defined as total current available for IREFIN and any external load. 4 Reference bandwidth is a function of external cap at NR pin. Refer to compensation section of data sheet for details. 5 Excludes internal reference drift. 6 Includes internal reference drift. 7 Measured as unbuffered voltage output (1 V range) with FS current into 50 load at IOUTB. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS * Parameter Positive Supply Voltage (V DD) Negative Supply Voltage (VEE) Analog-to-Other Grounds (REFCOM) Digital-to-Other Grounds (DCOM) Reference Output (REFOUT) Reference Input Current (IREFIN) Digital Inputs (DB0DB15, CLOCK) Analog Outputs (IOUTA, IOUTB) Maximum Junction Temperature Storage Temperature Lead Temperature with Respect to DCOM, REFCOM, LADCOM DCOM, REFCOM, LADCOM DCOM, LADCOM LADCOM, REFCOM REFCOM DCOM LADCOM Min 0.5 6.0 0.5 0.5 Max +6.0 +0.5 +0.5 +0.5 VDD + 0.5 +7.5 VDD + 0.5 +5.0 +150 +150 +300 Units V V V V V mA V V °C °C °C
0.5 2.0 65
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating for extended periods may affect device reliability.
ORDERING GUIDE
DB0DB15
Model AD768AR AD768ACHIPS AD768-EB
Package Description 28-Pin 300 mil SOIC Die AD768 Evaluation Board
Package Option R-28
tS
CLOCK
tH tLPW tPD tST
0.025%
IOUTA OR IOUTB
0.025%
Timing Diagram
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD768 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
3
AD768 WAFER TEST LIMITS1
Parameter Integral Nonlinearity Differential Nonlinearity2 Offset Error Gain Error Reference Voltage Positive Supply Current Negative Supply Current Power Dissipation
2
(TA = +25 C, VDD = +5.0 V, VEE = 5.0 V, IREFIN = 5 mA, unless otherwise noted)
AD768ACHIPS Limit ±8 ±6 ± 0.2 ± 1.0 ± 1.0 40 73 600 Units LSB max LSB max % FSR max % FSR max % of nom. 2.5 V max mA max mA max mW max
NOTES 1 Electrical test are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. 2 Limits extrapolated from testing of individual bit errors. 3 Die offers latch control pad. Edge triggered latches become level triggered when latch control and clock pads are high. 4 Die substrate is connected to V EE.
PIN DESCRIPTIONS
Pin No. 1 2 3 4 5 6 7 814 15 16 1723 24 25 26 27 28
Symbol IOUTA NR REFOUT NC REFCOM IREFIN DB0 DB1DB7 DCOM CLOCK DB8DB14 DB15 V DD V EE IOUTB LADCOM
Type AO AI AO NC P AI DI DI P DI DI DI P P AO P
Name and Function DAC Current Output. Full-scale current when all data bits are 1s. Noise Reduction Node. Add capacitor for noise reduction. Reference Output Voltage. Nominal value is 2.5 V. No Connect. Reserved for internal use. Reference Ground. Reference Input Current. Nominal is 5 mA. DAC full-scale is 4× this current. Data Bit 0 (LSB). Data Bits 17. Digital Ground. Clock Input. Data latched on positive edge of clock. Data Bits 814. Data Bit 15 (MSB). Positive Supply Voltage. Nominal is +5 V. Negative Supply Voltage. Nominal is 5 V. Complementary DAC Current Output. Full-scale current when all data bits are 0s. DAC Ladder Common.
Type: AI = Analog Input; DI = Digital Input; AO = Analog Output; P = Power.
PIN CONFIGURATION
VDD VDD
DICE CHARACTERISTICS 3, 4
DB15 DB14 DB13 DB12 DB11 DB10
IOUTA 1 NR 2 REFOUT 3 NC 4 REFCOM 5 IREFIN 6 (LSB) DB0 7
28 LADCOM 27 IOUTB 26 VEE (5V) 25 VDD (+5V) 24 DB15 (MSB)
VEE VEE DB9 DB8
AD768
23 DB14
IOUTB LADCOM IOUTA NR REFOUT NC REFCOM IREFIN DB0 DB1 DB2 DB3 DB4
CLOCK LATCH CONTROL DCOM DB7 DB6 DB5
TOP VIEW 22 DB13 (Not to Scale) DB1 8 21 DB12 DB2 9 DB3 10 DB4 11 DB5 12 DB6 13 DB7 14 20 DB11 19 DB10 18 DB9 17 DB8 16 CLOCK 15 DCOM
NC = NO CONNECT
Die Size: 0.1106 × 0.1417 inch, 15,672 sq. mils (2.81 × 3.60 mm, 10.116 sq. mm)
4
REV. B
AD768
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL) Temperature Drift
Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
Temperature drift is specified as the maximum change from the ambient (+25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree C. For reference drift, the drift is reported in ppm per degree C.
Power Supply Rejection
DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A D/A converter is monotonic if the output either increases or remains constant as the digital input increases.
Offset Error
The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages.
Settling Time
The deviation of the output current from the ideal of zero is called offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s.
Gain Error
The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition.
Spurious-Free Dynamic Range
The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. The ideal output current span is 4× the current applied to the IREFIN pin.
Output Compliance Range
The difference, in dB, between the rms amplitude of the input signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB).
Glitch Impulse
The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance.
CREFCOMP 1µF NC +5V 1µF
5 25 4 3 6
Asymmetrical switching times in a DAC give rise to undesired output transients which are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-sec.
RREF 500 REFIN 5mA RLAD 1k IOUTA IOUTB RLAD 1k LADCOM
1 27
REFOUT
VDD REFCOM NR VEE
+2.5V REF
IOUTA IOUTB 50 RLOAD 50
1µF 1µF CNR 5V
26 2
28
15 DCOM
AD768
MSB DECODE & LATCHES
24 23 22 21 20 19 18
SEGMENTED CURRENT SOURCES
CLOCK
CLOCK
16
CURRENT SOURCES AND R-2R LADDER
LATCHES LOWER 12 BITS
17 14 13 12 11 10 9 8 7
DB15
DB14
DB13
DB11
DB3
DB7
DB2
DB1
DB10
DB9
DB12
DB8
DB6
DB5
Figure 1. Functional Block Diagram and Basic Hookup
FUNCTIONAL DESCRIPTION
The AD768 is a current-output DAC with a nominal full-scale current of 20 mA and a 1 k output impedance. Differential outputs are provided to support single-ended or differential applications. The DAC architecture combines segmented current sources for the top four bits (MSBs) and a 1 k R-2R ladder for the lower 12 bits (LSBs). The DAC current sources are implemented with laser-trimmable thin film resistors for excellent dc linearity. A proprietary switching technique is utilized to reduce glitch energy and maximize dynamic accuracy.
The digital interface offers CMOS compatible edge-triggered input latches that interface readily to CMOS logic and supports clock rates up to 40 MSPS. A temperature compensated 2.5 V bandgap reference is integrated on-chip to drive the AD768 reference input current with the use of a single external resistor. The functional block diagram in Figure 1 is a simple representation of the internal circuitry to aid the understanding of the AD768's operation. The DAC transfer function is described, and followed by a detailed description of each key portion of the circuit. Typical circuit configurations are shown in the section APPLYING THE AD768.
REV. B
5
DB4
DB0
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