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Details, datasheet, quote on part number:AD7680BRM
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Datasheet text preview:
PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES Fast Throughput Rate: 100kSPS Specified for VDD of 2.5 V to 5.25 V Low Power: 2.5mW typ at 100kSPS with 3V Supplies 15mW typ at 100kSPS with 5V Supplies Wide Input Bandwidth: 85dB SNR at 10kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High Speed Serial Interface SPI/QSPI/µWire/DSP Compatible µ Standby Mode: 0.5 µA max 6-Lead SOT-23, and 8-Lead µSOIC Packages APPLICATIONS Battery-Powered Systems Personal Digital Assistants Medical Instruments Mobile Communications Instrumentation and Control Systems Remote Data Acquisition Systems High-Speed Modems Optical Sensors
3V, 3mW, 100kSPS, 16-Bit ADC in 6 Lead SOT-23 AD7680
F U N C T I O N A L BLOCK DIAGRAM
V DD
VI N
T/ H
16-BI T SUCCE SSI VE AP PRO XI MAT IO N A DC
AD7680
SC LK CON TRO L L OG I C SD ATA CS
G ND
P R O D U C T HIGHLIGHTS
1. First 16-Bit ADC in a SOT-23 package. 2. High Throughput with Low Power Consumption 3 . Flexible Power/Serial Clock Speed Management The conversion rate is determined by the serial clock allowing the conversion time to be reduced through the serial clock speed increase. This allows the average power cunsumption to be reduced when a powerdown mode is used while not converting. The part also features a shutdown mode to maximize power efficiency at lower throughput rates. Power consumption is 0.5µA max when in shutdown. 4. Reference derived from the power supply. 5 . No Pipeline Delay The part features a standard successive-approximation ADC with accurate control of the sampling instant via a CS input and once off conversion control.
G E N E R A L DESCRIPTION
The AD7680 is a 16-bit, fast, low power, successive-approximation ADC. The part operates from a single 2.5 V to 5.25 V power supply and features throughput rates up to 100kSPS. The part contains a low-noise, wide bandwidth track/hold amplifier which can handle input frequencies in excess of 100kHz. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and the conversion is also initiated at this point. There are no pipelined delays associated with the part. The AD7860 uses advanced design techniques to achieve very low-power dissipation at fast throughput rates. The reference for the part is taken internally from VDD. This allows the widest dynamic input range to the ADC. Thus the analog input range for the part is 0 to VDD. The conversion rate is determined by the SCLK frequency.
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One Technology Way, P O. Box 9106, Norwood, MA 02062-9106, U.S.A. . Te l : 781/329-4700 World Wide Web Site: http://www.analog.com F a x : 781/326-8703 Analog Devices, Inc., 2002
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
f = 2.5MHz, f AD7680SPECIFICATIONS1 (nVoted=; T+2.5TV toto+5.25, V,unless otherwise noted.) = 100Ksps unless otherwise = T
DD SCLK SAMPLE A MIN MAX
PRELIMINARY TECHNICAL DATA
B Version1 3V 5V 81 82 85 -95 -99 Units
Parameter D Y N A M I C PERFORMANCE Signal to Noise + Distortion (SINAD)2 Signal to Noise Ratio (SNR)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD) 2 Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth D C ACCURACY No missing Codes Integral Nonlinearity3 Offset Error3 Gain Error3 A N A L O G INPUT Input Voltage Ranges DC Leakage Current Input Capacitance L O G I C INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN2,3 L O G I C OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance2,3 Output Coding C O N V E R S I O N RATE Conversion Time Track/Hold Acquisition Time Throughput Rate P O W E R REQUIREMENTS VD D ID D Normal Mode(Static) Normal Mode (Operational) Full Power-Down Mode Power Dissipation4 Normal Mode (Operational) Full Power-Down
Test Conditions/Comments FIN = 10kHz Sine Wave
83 86 -95 -99
dB dB dB dB dB
min min typ typ typ
-90 -90 -90 -90 10 10 30 30 TBD TBD 15 ±4 ±5 ±5 14 ±4 ±5 ±10
dB typ dB typ ns max ps typ MHz typ @ 3 dB MHz typ @ 0.1 dB Bits min L S B max L S B max L S B max Volts µ A max pF typ V min V max µA max p F max
0 to VDD ±1 30 2.4 0.4 ±1 10 2.4 0.8 ±1 10
Typically 10 nA, VIN = 0 V or VDD
VDD -0.2 V min ISOURCE = 200 µA; VDD = 2.5 V to 5.25 V 0.4 V max ISINK =200 µA ±1 µ A max 10 p F max Straight (Natural) Binary 8 9.6 500 400 100 +2.5/+5.25 0.5 1 0.5 2 3.5 0.5 µ s max µ s max ns max ns max kSPS V min/max mA typ mA max µA max Digital I/Ps = 0V or VDD. SCLK on or off. FSAMPLE = 100 kSPS SCLK on or off. 20 SCLK cycles with SCLK at 2.5MHz 24 SCLK cycles with SCLK at 2.5MHz Full-scale step input Sine wave input <= 10KHz See Serial Interface Section
3 1.5
17.5 2.5
mW max µW max
FSAMPLE = 100 kSPS
NOTES 1 T e m p e r a t u r e ranges as follows: B Version: 40°C to +85°C. 2 S e e Terminology. 3 S a m p l e tested @ +25°C to ensure compliance. 4 S e e POWER VERSUS THROUGHPUT RATE section. S p e c i f i c a t i o n s subject to change without notice.
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PRELIMINARY TECHNICAL DATA AD7680 TIMING SPECIFICATIONS1
Parameter 3V fSCLK
2
(VDD = +2.5 V to +5.25 V; TA = TMIN to TMAX, unless otherwise noted.)
Limit at TMIN, TMAX Units 5V 10 2.5 2 0 x tS C L K 50 10 10 20 40 0.4tSCLK 0.4tSCLK 10 25 1 k H z min M H z max min ns min ns ns ns ns ns ns ns ns µs min min max max min min min max typ 10 2.5 2 0 x tS C L K 50 10 10 20 40 0.4tSCLK 0.4tSCLK 10 25 1 Description
tCONVERT tquiet t1 t2 t33 t43 t5 t6 t7 t84 tpower-up5
Minimum Quiet Time required between Bus Relinquish and start of next conversion Minimum CS Pulse Width CS to SCLK Setup Time Delay from CS Until SDATA 3-State Disabled Data Access Time After SCLK Falling Edge SCLK Low Pulse Width SCLK High Pulse Width SCLK to Data Valid Hold Time SCLK falling Edge to SDATA High Impedance Power up time from Full Power-down.
NOTES 1 Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 Volts. 2 Mark/Space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V. 4 t8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 5 See Power-up Time section. Specifications subject to change without notice.
A B S O L U T E MAXIMUM RATINGS 1
(TA = +25°C unless otherwise noted)
V DD to GND ........0.3 V to +7 V Analog Input Voltage to GND....... 0.3 V to VDD + 0.3 V Digital Input Voltage to GND........0.3 V to +7 V Digital Output Voltage to GND.....0.3 V to VDD + 0.3 V Input Current to Any Pin Except Supplies2 .........±10 mA O p e r a t i n g Temperature Range C o m m e r c i a l (B Version)............40°C to +85°C S t o r a g e Temperature Range.....65°C to +150°C J u n c t i o n Temperature.......+150°C S O T - 2 3 Package, Power Dissipation.........450 mW JA Thermal Impedance.......229.6°C/W JC Thermal Impedance.........91.99°C/W µSOIC Package, Power Dissipation.........450 mW JA Thermal Impedance.......205.9°C/W JC Thermal Impedance........ 43.74°C/W L e a d Temperature, Soldering V a p o r Phase (60 secs)..215°C I n f a r e d (15 secs)..........220°C ESD..........3.5kV
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch up.
200µA
IO L
TO OUTPUT P IN CL 50pF 200µA
+1.6V
IOH
Figure 1. Load Circuit for Digital Output Timing Specifications
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7680 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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PRELIMINARY TECHNICAL DATA AD7680
P I N FUNCTION DESCRIPTION
Pin Mnemonic VDD GND VIN SCLK SDATA
Function Power Supply Input. The VDD range for the AD7680 is from +2.5V to +5.25V. Analog Ground. Ground reference point for all circuitry on the AD7680. All analog input signals should be referred to this GND voltage. Analog Input. Single-ended analog input channel. The input range is 0 to VDD. Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the AD7680's conversion process. Data Out. Logic Output. The conversion result from the AD7680 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7680 consists of 4 leading zeros followed by 16 bits of conversion data which is provided MSB first. This will be followed by 4 trailing zeroes if CS is held low for a total of 24 SCLK cycles. See serial Interface section. Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7680 and framing the serial data transfer. No Connect. This pin should be left unconnected.
CS NC
A D 7 6 8 0 PIN CONFIGURATIONS
SOT-23
µSOIC
VD D G ND VI N
1
6
CS S D AT A S C LK
VD D 1 GN D GN D
2 3
8
CS SD ATA NC SC L K
A D768 0
2 3
T O P V IE W ( No t t o S c al e)
5 4
A D7 680
7
T O P V IEW 6 ( Not to S cal e)
5
VI N 4
N C = N O C O N N EC T
O R D E R I N G GUIDE
Model
Range
Linearity Package Error (LSB)1 Option2 Branding ±2 typ ±2 typ RT-6 RM-8 CQB CQB
AD7680BRT -40°C to +85°C AD7680BRM -40°C to +85°C
NOTES 1 Linearity error here refers to integral nonlinearity 2 RT = SOT-23. 2 RM = µSOIC.
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PRELIMINARY TECHNICAL DATA AD7680
TERMINOLOGY I n t e g r a l Nonlinearity T o t a l Harmonic Distortion
This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 LSB below the first code transition, and full scale, a point 1/2 LSB above the last code transition.
D i f f e r e n t i a l Nonlinearity
Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7860, it is defined as:
THD (dB ) = 20 log V2 +V3 +V 4 +V5 +V 6 V1
2 2 2 2 2
This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.
Offset Error
where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through the sixth harmonics.
Peak Harmonic or Spurious Noise
This is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e AGND + 1LSB
G a i n Error
This is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e., VREF 1 LSB) after the offset error has been adjusted out.
T r a c k / H o l d Acquisition Time
Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise peak.
I n t e r m o d u l a t i o n Distortion
The track/hold amplifier returns into track mode at the end of conversion. Track/Hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within ±0.5 LSB, after the end of conversion. See serial interface timing section for more details.
Signal to (Noise + Distortion) Ratio
With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa fb), while the third order terms include (2fa + fb), (2fa fb), (fa + 2fb) and (fa 2fb). The AD7680 is tested using the CCIF standard where two input frequencies nearthe top end of the input bandwidth are used. In this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs.
This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02 N + 1.76) dB Thus for a 16-bit converter, this is 98 dB.
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