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Details, datasheet, quote on part number:AD7721SQ
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| Part: | AD7721SQ |
| Category: | Data Conversion => ADC (Analog to Digital Converters) => 10-14 bit |
| Description: | CMOS, 12-/16-Bit, 312.5 KHz/468.75 KHZ Sigma-delta ADC |
| Company: | Analog Devices |
| Datasheet: | Download AD7721SQ datasheet File size : 266 kB |
| Request For quote: | Find where to buy AD7721SQ
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Datasheet text preview:
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FEATURES 16-Bit Sigma-Delta ADC 468.75 kHz Output Word Rate (OWR) No Missing Codes Low-Pass Digital Filter High Speed Serial Interface Linear Phase 229.2 kHz Input Bandwidth Power Supplies: AVDD, DVDD: +5 V 5% Standby Mode (70 W) Parallel Mode (12-Bit/312.5 kHz OWR)
CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADC AD7721
FUNCTIONAL BLOCK DIAGRAM
AGND DGND DGND DSUBST VIN1 VIN2 DVAL/SYNC CS RD WR DRDY SDATA/DB11 CONTROL LOGIC RFS/DB10 DB9 CLK AGND AVDD DVDD
AD7721
12-BIT A/D CONVERTER MODULATOR FIR FILTER REFIN
STBY/DB0 CAL/DB1 UNI/DB2
GENERAL DESCRIPTION
The AD7721 is a complete low power, 12-/16-bit, sigma-delta ADC. The part operates from a +5 V supply and accepts a differential input of 0 V to 2.5 V or ± 1.25 V. The analog input is continuously sampled by an analog modulator at twice the clock frequency eliminating the need for external sample-andhold circuitry. The modulator output is processed by two finite impulse response (FIR) digital filters in series. The on-chip filtering reduces the external antialias requirements to first order in most cases. Settling time for a step input is 97.07 µs while the group delay for the filter is 48.53 µs when the master clock equals 15 MHz. The AD7721 can be operated with input bandwidths up to 229.2 kHz. The corresponding output word rate is 468.75 kHz. The part can be operated with lower clock frequencies also. The sample rate, filter corner frequency and output word rate will be reduced also, as these are proportional to the external clock frequency. The maximum clock frequencies in parallel mode and serial mode are 10 MHz and 15 MHz respectively.
DB3
DB4
SYNC/ DB6 DB5
SCLK/ DB8 DB7
Use of a single bit DAC in the modulator guarantees excellent linearity and dc accuracy. Endpoint accuracy is ensured by onchip calibration of offset and gain. This calibration procedure minimizes the part's zero-scale and full-scale errors. The output data is accessed from the output register through a serial or parallel port. This offers easy, high speed interfacing to modern microcontrollers and digital signal processors. The serial interface operates in internal clocking (master) mode, the AD7721 providing the serial clock. CMOS construction ensures low power dissipation while a power-down mode reduces the power consumption to only 100 µW.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1997
5%; DGND = 0 V, AD7721SPECIFICATIONS1 (fAV = =15+5 V REFIN DV+2=.5+5 TV = T5%;toAGND ,=unless otherwise noted) MHz, = V; T
DD DD CLK A MIN MAX
Parameter SERIAL MODE ONLY STATIC PERFORMANCE Resolution Minimum Resolution for Which No Missing Codes Is Guaranteed Differential Nonlinearity Integral Nonlinearity DC CMRR Offset Error2 Unipolar Mode Bipolar Mode Full-Scale Error 2, 3 Unipolar Mode Bipolar Mode Unipolar Offset Drift Bipolar Offset Drift ANALOG INPUTS Signal Input Span (VIN1VIN2) Bipolar Mode Unipolar Mode Maximum Input Voltage Minimum Input Voltage Input Sampling Capacitance Input Sampling Rate Differential Input Impedance REFERENCE INPUTS V REFIN REFIN Input Current DYNAMIC SPECIFICATIONS Signal to (Noise + Distortion) Total Harmonic Distortion Frequency Response 0 kHz210 kHz 229.2 kHz 259.01 kHz to 14.74 MHz CLOCK CLK Duty Ratio VCLKH, CLK High Voltage VCLKL, CLK Low Voltage LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES A V DD D V DD IDD (Total from AVDD, DVDD) Power Consumption Power Consumption
A Version
S Version
Units
Test Conditions/Comments
16 12 ±8 ± 16 70 ± 3.66 ± 3.66 ± 4.88 ± 4.88 0.05 0.04
16 12 ±8 ± 16 70 ± 3.66 ± 3.66 ± 4.88 ± 4.88 0.05 0.04
Bits Bits min LSB typ LSB max dB min mV max mV max mV max mV max mV/°C typ mV/°C typ
Guaranteed 12 Bits Monotonic
16-Bit Operation Bipolar Mode Typically 0.61 mV Typically 0.61 mV Typically 0.61 mV Typically 1.22 mV
± V R E F I N/ 2 0 to VREFIN AV DD 0 1.6 2 f CLK 20.8 2.4 to 2.6 200 74 78 ± 0.05 3 72 45 to 55 0.7 × DVDD 0.3 × DVDD 2.0 0.8 10 10 4.0 0.4 4.75/5.25 4.75/5.25 28.5 150 100
± V R E F I N/ 2 0 to VREFIN A V DD 0 1.6 2 f CLK 20.8 2.4 to 2.6 200 74 78 ± 0.05 3 72 45 to 55 0.7 × DVDD 0.3 × DVDD 2.0 0.8 10 10 4.0 0.4 4.75/5.25 4.75/5.25 28.5 150 100
Volts max Volts max Volts Volts pF typ MHz k typ V min/V max µA typ dB min dB max dB max dB min dB min % max V min V max V min V max µA max pF max V min V max V min/V max V min/V max mA max mW max µW max
U N I = VI H U N I = VI L
Guaranteed by Design With 15 MHz on CLK Pin
Input Bandwidth 0 kHz to 210 kHz Input Bandwidth 0 kHz to 229.2 kHz
For Specified Operation CLK Uses CMOS Logic
|IOUT| 200 µA |IOUT| 1.6 mA
Digital Inputs Equal to 0 V or DVDD Active Mode Standby Mode
NOTES 1 Operating temperature range is as follows: A Version: 40°C to +85°C; S Version: 55°C to +125°C. 2 Applies after calibration at temperature of interest. 3 Full-scale error applies to both positive and negative full-scale error. The ADC gain is calibrated w.r.t. the voltage on the REFIN pin. Specifications subject to change without notice.
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REV. A
SPECIFICATIONS1 (RAEVFIN==+52V.5 V;5%;=DV + TT
DD A
= +5 V 5%; AGND = DGND = 0 V, fCLK = 10 MHz, to TMAX, unless otherwise noted) MIN
DD
AD7721
Parameter PARALLEL MODE ONLY STATIC PERFORMANCE Resolution Minimum Resolution for Which No Missing Codes Is Guaranteed Differential Nonlinearity Integral Nonlinearity DC CMRR Offset Error2 Unipolar Mode Bipolar Mode Full-Scale Error 2, 3 Unipolar Mode Bipolar Mode Unipolar Offset Drift Bipolar Offset Drift ANALOG INPUTS Signal Input Span (VIN1VIN2): Bipolar Mode Unipolar Mode Maximum Input Voltage Minimum Input Voltage Input Sampling Capacitance Input Sampling Rate Differential Input Impedance REFERENCE INPUTS V REFIN REFIN Input Current DYNAMIC SPECIFICATIONS Signal to (Noise + Distortion) Total Harmonic Distortion Frequency Response 0 kHz140 kHz 152.8 kHz 172.67 kHz to 9.827 MHz CLOCK CLK Duty Ratio VCLKH, CLK High Voltage VCLKL, CLK Low Voltage LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL , Output Low Voltage POWER SUPPLIES A V DD D V DD IDD (Total from AVDD, DVDD) Power Consumption Power Consumption
A Version
S Version
Units
Test Conditions/Comments
12 12 ± 1/2 ± 1/2 70 ± 3.66 ± 3.66 ± 4.88 ± 4.88 0.04 0.035
12 12 ± 1/2 ± 1/2 70 ± 3.66 ± 3.66 ± 4.88 ± 4.88 0.04 0.035
Bits Bits min LSB typ LSB typ dB min mV max mV max mV max mV max mV/°C typ mV/°C typ
Guaranteed 12 Bits Monotonic 12-Bit Operation Bipolar Mode Typically 0.61 mV Typically 0.61 mV Typically 0.61 mV Typically 1.22 mV
± V REFIN / 2 0 to VREFIN A V DD 0 1.6 2 f CLK 31.25 2.4 to 2.6 200 70 78 ± 0.05 3 72 45 to 55 0.7 × DVDD 0.3 × DVDD 2.0 0.8 10 10 4.0 0.4 4.75/5.25 4.75/5.25 28.5 150 100
± V REFIN / 2 0 to VREFIN A V DD 0 1.6 2 f CLK 31.25 2.4 to 2.6 200 70 78 ± 0.05 3 72 45 to 55 0.7 × DVDD 0.3 × DVDD 2.0 0.8 10 10 4.0 0.4 4.75/5.25 4.75/5.25 28.5 150 100
Volts max Volts max Volts Volts pF typ MHz k typ V min/V max µA typ dB min dB max dB max dB min dB min % max V min V max V min V max µA max pF max V min V max V min/V max V min/V max mA max mW max µW max
U N I = V IH U N I = V IL
Guaranteed by Design With 10 MHz on CLK Pin
Input Bandwidth 0 kHz to 140 kHz Input Bandwidth 0 kHz to 152.8 kHz
For Specified Operation CLK Uses CMOS Logic
|IOUT| 200 µA |IOUT| 1.6 mA
Digital Inputs Equal to 0 V or DVDD
Active Mode Standby Mode
NO TES 1 Operating temperature range is as follows: A Version: 40°C to +85°C; S Version: 55°C to +125°C. 2 Applies after calibration at temperature of interest. 3 Full-scale error applies to both positive and negative full-scale error. The ADC gain is calibrated w.r.t. the voltage on the REFIN pin. Specifications subject to change without notice.
REV. A
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AD7721 TIMING CHARACTERISTICS1, 2
Parameter Serial Interface fC L K 3 tCLK LO tCLK HI t1 t2 4 t3 t4 t5 t6 t7 t8 5 t9 Parallel Interface fC L K 3 tCLK LO tCLK HI Read Operation t10 t11 t12 Write Operation t13 t14 t15
(AVDD= +5 V 5%; DVDD= +5 V unless otherwise noted)
Units kHz min MHz max ns min ns min ns nom ns min ns max ns nom ns nom ns max ns min ns min ns max ns nom kHz min MHz max ns min ns min ns nom ns max ns nom ns min ns min ns min
5%; AGND = DGND = 0 V, REFIN = +2.5 V
Limit at TMIN, TMAX (A, S Versions) 100 15 0.45 × tCLK 0.45 × tCLK tCLK tCLK HI 10 20 tCLK HI tCLK LO 25 0 0 20 3 2 × t CLK 100 10 0.45 × tCLK 0.45 × tCLK 2 × t CLK 30 3 2 × t CLK 35 20 0
Conditions/Comments Master Clock Frequency 15 MHz for Specified Performance Master Clock Input Low Time Master Clock Input High Time DRDY High Time RFS Low to SCLK Falling Edge Setup Time RFS Low to Data Valid Delay SCLK High Pulse Width SCLK Low Pulse Width SCLK Rising Edge to Data Valid Delay RFS to SCLK Falling Edge Hold Time Bus Relinquish Time after Rising Edge of RFS Period between Consecutive DRDY Rising Edges Master Clock Frequency 10 MHz for Specified Performance Master Clock Input Low Time Master Clock Input High Time DRDY High Time Data Access Time after Falling Edge of DRDY Period between Consecutive DRDY Rising Edges WR Pulse Width Data Valid to WR High Setup Time Data Valid to WR High Hold Time
NOTES The timing is measured with a load of 50 pF on SCLK and DRDY. SCLK can be operated with a load capacitance of 50 pF maximum. 1 Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 All digital outputs are timed with the load circuit below and, except for t 2, are defined as the time required for an output to cross 0.8 V or 2 V, whichever occurs last. 3 The AD7721 is production tested with f CLK at 10 MHz for parallel mode operation and at 15 MHz for serial mode operation. However, it is guaranteed by characterization to operate with CLK frequencies down to 100 kHz. 4 t2 is the time from RFS crossing 1.6 V to SCLK crossing 0.8 V. 5 t8 and t15 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown below. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the Timing Characteristics is the true bus relinquish time of the part and, as such, is independent of external bus loading capacitance.
1.6mA
IOL
TO OUTPUT PIN
+1.6V CL 50pF 200 A IOH
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
4
REV. A
AD7721
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25°C unless otherwise stated)
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . 0.3 V to +0.3 V Digital Input Voltage to DGND . . . 0.3 V to DVDD + 0.3 V Analog Input Voltage to AGND . . . . 0.3 V to AVDD + 0.3 V Input Current to Any Pin Except Supplies2 . . . . . . . ± 10 mA Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . . 40°C to +85°C Extended (S Version) . . . . . . . . . . . . . . . . 55°C to +125°C Storage Temperature Range . . . . . . . . . . . . 65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C Plastic Package JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 74°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . Cerdip Package JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . Lead Temperature, Soldering (10 sec) . . . . . . . . . . SOIC Package JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .
+260°C 51°C/W +300°C 72°C/W +215°C +220°C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latchup.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this device features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
PIN CONFIGURATION
Model AD7721AN AD7721AR AD7721SQ
Temperature Range 40°C to +85°C 40°C to +85°C 55°C to +125°C
Package Option* N-28 R-28 Q-28
SCLK/DB7 1 DB8 2 DB9 3 RFS/DB10 4 SDATA/DB11 5 DGND 6 28 DB6 27 RD 26 WR 25 DVAL/SYNC 24 AGND
*N = Plastic DIP; R = 0.3" Small Outline IC (SOIC); Q = Cerdip.
AD7721
TOP VIEW 23 VIN2 DSUBST 7 (Not to Scale) 22 VIN1 DGND 8 STBY/DB0 9 DVDD 10 CAL/DB1 11 UNI/DB2 12 DB3 13 DB4 14 21 REFIN 20 AGND 19 AVDD 18 CS 17 CLK 16 DRDY 15 SYNC/DB5
REV. A
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