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Details, datasheet, quote on part number:AD7722AS
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Datasheet text preview:
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FEATURES 16-Bit Sigma-Delta ADC 64 Oversampling Ratio Up to 220 kSPS Output Word Rate Low-Pass, Linear Phase Digital Filter Inherently Monotonic On-Chip 2.5 V Voltage Reference Single Supply +5 V High Speed Parallel or Serial Interface
16-Bit, 195 kSPS CMOS, Sigma-Delta ADC AD7722
FUNCTIONAL BLOCK DIAGRAM
DGND DVDD AGND AVDD REF1
AD7722
2.5V REFERENCE
REF2
VIN(+) VIN()
16-BIT A/D CONVERTER MODULATOR FIR FILTER
P/S CAL RESET SYNC CS DVAL/RD CFMT/DRDY DB0 DB1 DB2 CONTROL LOGIC
CLOCK CIRCUITRY
XTAL CLKIN UNI DB15 DB14 DB13 DB12 DB11 DB10 DB9/FSO
GENERAL DESCRIPTION
The AD7722 is a complete low power, 16-bit, sigma-delta ADC. The part operates from a +5 V supply and accepts a differential input voltage range of 0 V to +2.5 V or ± 1.25 V centered around a common-mode bias. The AD7722 provides 16-bit performance for input bandwidths up to 90.625 kHz. The part provides data at an output word rate of 195.3 kHz. The analog input is continuously sampled by an analog modulator eliminating the need for external sample-and-hold circuitry. The modulator output is processed by two Finite Impulse Response (FIR) digital filters in series. The on-chip filtering reduces the external antialias requirements to first order, in most cases. The group delay for the filter is 215.5 µs, while the settling time for a step input is 431 µs. The sample rate, filter corner frequency, and output word rate are set by an external clock that is nominally 12.5 MHz. Use of a single bit DAC in the modulator guarantees excellent linearity and dc accuracy. Endpoint accuracy is ensured by onchip calibration. This calibration procedure minimizes the zeroscale and full-scale errors.
DB3/ TSI
DB4/ DB5/ DB6/ DB7/ DB8/ DOE SFMT FSI SCO SDO
Conversion data is provided at the output register through a flexible serial port or a parallel port. This offers 3-wire, high speed interfacing to digital signal processors. The serial interface operates in an internal clocking (master) mode, whereby an internal serial data clock and framing pulse are device outputs. Additionally, two AD7722s can be configured with the serial data outputs connected together. Each converter alternately transmits its conversion data on a shared serial data line. The part provides an accurate on-chip 2.5 V reference. A reference input/output function is provided to allow either the internal reference or an external system reference to be used as the reference source for the part. The AD7722 is available in a 44-pin PQFP package and is specified over the industrial temperature range from 40°C to + 8 5° C .
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1996
AND772LowSPECI=FICMHz;TFIO195.3 1 (AV REF2AV= +2.5+5 VT = 5%; to T =; +5 V otherwise noted) = DGND = 0 V; 2 or High; f 12.5 A = NSkSPS; = = V; T DV unless 5%; AGND = AGND1 U I = Logic
DD DD1 DD CLKLIN S A MIN MAX
Parameter DYNAMIC SPECIFICATIONS2 Bipolar Mode, UNI = VINH Signal to (Noise + Distortion)3 Total Harmonic Distortion3 Spurious Free Dynamic Range Unipolar Mode, UNI = VINL Signal to (Noise + Distortion)3 Total Harmonic Distortion3 Spurious Free Dynamic Range Intermodulation Distortion AC CMRR Digital Filter Response Pass-Band Ripple Cutoff Frequency Stop-Band Attenuation ANALOG INPUTS Full-Scale Input Span Bipolar Mode Unipolar Mode Absolute Input Voltage Input Sampling Capacitance Input Sampling Rate Differential Input Impedance CLOCK CLKIN Mark Space Ratio REFERENCE REF1 Output Voltage REF1 Output Voltage Drift REF1 Output Impedance Reference Buffer Offset Voltage Using Internal Reference REF2 Output Voltage REF2 Output Voltage Drift Using External Reference REF2 Input Impedance External Reference Voltage Range STATIC PERFORMANCE Resolution Differential Nonlinearity Integral Nonlinearity After Calibration Offset Error4 Gain Error4, 5 Without Calibration Offset Error Gain Error5 Offset Error Drift Gain Error Drift
Test Conditions/Comments VCM = 2.5 V, VIN(+) = VIN() =1.25 V pk-pk or, VIN() =1.25 V, VIN(+) = 0 to 2.5 Input Bandwidth 0 kHz90.625 kHz Input Bandwidth 0 kHz100 kHz, fCLKIN = 14 MHz Input Bandwidth 0 kHz90.625 kHz Input Bandwidth 0 kHz100 kHz, fCLKIN = 14 MHz Input Bandwidth 0 kHz90.625 kHz Input Bandwidth 0 kHz100 kHz, fCLKIN = 14 MHz VIN() = 0 V, VIN(+) = 0 to 2.5 Input Bandwidth 0 kHz90.625 kHz Input Bandwidth 0 kHz97.65 kHz Input Bandwidth 0 kHz97.65 kHz VIN(+) = VIN() = 2.5 V pk-pk VCM = 1.25 V to 3.75 V, 20 kHz 0 kHz90.625 kHz
Min
A Version Typ
Max
Units
86/84.5 84.5/83
90 90/88 88/86 90 88
dB dB dB dB dB dB dB dB dB dB dB
84.5/83
88 89/87 90 93 96 ± 0.005
96.92 104.6875 kHz to 12.395 MHz V I N ( + ) VI N ( ) U N I = VINH U N I = VI N L VIN(+) and VIN() Guaranteed by Design 90
dB kHz dB
VREF2/2 0 0 2 2 × fCLKIN 1/8E-09 × fCLKIN 45 2.32 2.47 60 3
+VREF2/2 VR E F 2 A VD D
V V V pF Hz k % V p p m /° C k mV V p p m /° C k V Bits LSB LSB mV % FSR mV % FSR LSB/°C LSB/°C LSB/°C
55 2.62
Offset Between REF1 and REF2 2.32 2.47 60
± 12 2.62
REF1 = AGND Applied to REF1 or REF2
2.32 16
1/16E-09 × fCLKIN 2.5 2.62
Guaranteed Monotonic
± 0.5 ±2
±1 ±3 ± 0.6
±6 ± 0.6 ±1 REF2 Is an Ideal Reference, REF1 = AGND Unipolar Mode Bipolar Mode ±1 ± 0.5
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AD7722
Parameter LOGIC INPUTS (Excluding CLKIN) VINH, Input High Voltage VINL, Input Low Voltage CLOCK INPUT (CLKIN) VINH, Input High Voltage VINL, Input Low Voltage ALL LOGIC INPUTS IIN, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES AVDD, AVDD1 D VD D ID D Power Consumption VIN = 0 V to DVDD Test Conditions/Comments Min 2.0 0.8 4.0 0.4 ± 10 10 4.0 0.4 4.75 4.75 Total from AVDD and DVDD 5.25 5.25 75 375 A Version Typ Max Units V V V V µA pF V V V V mA mW
|IOUT| = 200 µA |IOUT| = 1.6 mA
NOTES 1 Operating temperature range is as follows : A Version ; 40 °C to +85°C. 2 Measurement Bandwidth = 0.5 × FS; Input Level = 0.05 dB. 3 TA = +25°C to +85°C/TA = TMIN to TMAX. 4 Applies after calibration at temperature of interest. 5 Gain Error excludes reference error. The ADC gain is calibrated w.r.t. the voltage on the REF2 pin. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
ORDERING GUIDE
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 7 V AVDD, AVDD1 to AGND . . . . . . . . . . . . . . . . . . 0.3 V to 7 V AVDD, AVDD1 to DVDD . . . . . . . . . . . . . . . . . . . 1 V to +1 V AGND, AGND1 to DGND . . . . . . . . . . . . . 0.3 V to +0.3 V Digital Inputs to DGND . . . . . . . . . . 0.3 V to DVDD + 0.3 V Digital Outputs to DGND . . . . . . . . . 0.3 V to DVDD + 0.3 V VIN(+), VIN() to AGND . . . . . . . . . . 0.3 V to AVDD + 0.3 V REF1 to AGND . . . . . . . . . . . . . . . . 0.3 V to AVDD + 0.3 V REF2 to AGND . . . . . . . . . . . . . . . . 0.3 V to AVDD + 0.3 V DGND, AGND1, AGND2 . . . . . . . . . . . . . . . . . . . . . ± 0.3 V Operating Temperature Range . . . . . . . . . . . 40°C to +85°C Storage Temperature Range . . . . . . . . . . . . 65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 95°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Model AD7722AS
Temperature 40°C to +85°C
Package
Package
44-Pin PQFP S-44
IOL 1.6mA TO OUTPUT PIN
+1.6V CL 50pF
IOH 200µA
Figure 1. Load Circuit for Timing Specifications
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7722 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD7722 TIMING SPECIFICATIONS f
CLKIN Frequency CLKIN Period (tCLK = 1/fCLK) CLKIN Low Pulse Width CLKIN High Pulse Width CLKIN Rise Time CLKIN Fall Time FSI Low Time FSI Setup Time FSI Hold Time CLKIN to SCO Delay SCO Period1 SCO Transition to FSO High Delay SCO Transition to FSO Low Delay SCO Transition to SDO Valid Delay SCO Transition from FSI2 SDO Enable Delay Time SDO Disable Delay Time DRDY High Time Conversion Time1 DRDY to CS Setup Time CS to RD Setup Time RD Pulse Width Data Access Time after RD Falling Edge3 Bus Relinquish Time after RD Rising Edge CS to RD Hold Time RD to DRDY High Time SYNC/RESET Input Pulse Width DVAL Low Delay from SYNC/RESET SYNC/RESET Low Time Before CLKIN Rising DRDY High Delay after SYNC/RESET Low DRDY Low Delay after SYNC/RESET Low1 DVAL High Delay after SYNC/RESET Low1 CAL Setup Time CAL Pulse Width Calibration Delay from CAL High Unipolar Input Calibration Time, (UNI = "0")1 Bipolar Input Calibration Time, (UNI = "1")1 Conversion Results Valid, (UNI = "0")1 Conversion Results Valid, (UNI = "1")1
(AVDD= +5 V 5%, DVDD = +5 V 5%, AGND = DGND = 0 V, CL = 50 pF, TA = TMIN to TMAX, CLKIN = 12.5 MHz, SFMT = Logic Low or High, CFMT = Logic Low or High)
Symbol fC L K t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t1 6 t17 t18 t19 t20 t21 t22 t23 t24 t25 t2 6 t27 t28 t29 t30 t31 t34 t35 t3 6 t37 t37 t38 t38 2 64 0 0 tCLK + 20 tCLK + 40 tCLK + 40 0 1 10 40 10 50 (8192 + 64) 8192 10 1 2 64 (3 × 8192 + 2 × 512) (4 × 8192 + 3 × 512) (3 × 8192 + 2 × 512 + 64) (4 × 8192 + 3 × 512 + 64) Min 0.3 0.067 0.45 × t1 0.45 × t1 5 5 2 20 20 2 4 4 3 30 10 10 10 8 2.5 45 30 Typ 12.5 0.08 Max 15 3.33 0.55 × t1 0.55 × t1 Units MHz µs ns ns tCLK ns ns ns tCLK ns ns ns tCLK ns ns tCLK tCLK ns ns ns ns ns ns tCLK ns ns ns ns tCLK tCLK ns tCLK tCLK tCLK tCLK tCLK tCLK
40
NOTES 1 Guaranteed by design. 2 Frame Sync is initiated on falling edge of CLKIN. 3 With RD synchronous to CLKIN t 22, can be reduced up to 1 t CLK.
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AD7722
64 CKLIN CYCLES CLKIN
SCO (CFMT = 0) 32 SCO CYCLES FSO (SFMT = 0)
SCO
VALID DATA FOR 16 SCO CYCLES
ZERO FOR LAST 16 SCO CYCLES
VALID
Figure 2a. Generalized Serial Mode Timing (FSI = Logic Low or High, TSI = DOE)
64 CKLIN CYCLES CLKIN
SCO (CFMT = 0) 32 SCO CYCLES FSO (SFMT = 1) LOW FOR 16 SCO CYCLES HIGH FOR LAST 16 SCO CYCLES
SCO
VALID DATA FOR 16 SCO CYCLES
ZERO FOR LAST 16 SCO CYCLES
VALID
Figure 2b. Generalized Serial Mode Timing (FSI = Logic Low or High, TSI = DOE)
t5
CLKIN 2.3V 0.8V
t4 t3
t2
t1 t6
FSI
t8
t9
SCO
t7
t9
t 10
Figure 3. Serial Mode Timing for Clock Input, Frame Sync Input and Serial Clock Output
CLKIN
t1
FSI
t 10
SCO
t 11
SFMT = LOGIC LOW(0) FSO
t 12
t 14
SDO D15 D14 D13 D1 D0
t 13
SCO
t 12
SFMT = LOGIC HIGH(1) FSO LOW FOR D15D0
t 11
t 13
SDO D15 D14 D13 D1 D0
Figure 4. Serial Mode Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output and Serial Data Output (CFMT = Logic Low, TSI = DOE)
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