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Details, datasheet, quote on part number:AD7723BS
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Datasheet text preview:
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FEATURES 16-Bit Sigma-Delta ADC 1.2 MSPS Output Word Rate 32/16 Oversampling Ratio Low-Pass and Band-Pass Digital Filter Linear Phase On-Chip 2.5 V Voltage Reference Standby Mode Flexible Parallel or Serial Interface Crystal Oscillator Single +5 V Supply
AVDD AGND VIN(+) VIN()
16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC AD7723
FUNCTIONAL BLOCK DIAGRAM
AD7723
2.5V REFERENCE REF2 REF1 DVDD DGND
MODULATOR
FIR FILTER
UNI HALF_PWR STBY MODE 1 MODE 2 SYNC DVDD / CS CFMT/ RD DGND/ DRDY DGND/DB0
XTAL CLOCK
XTAL_OFF XTAL CLKIN DGND/DB15 DGND/DB14 SCR/DB13 SLDR/DB12 SLP/DB11 TSI/DB10 FSO/DB9
CONTROL LOGIC
DGND/ DGND/ DGND/ DOE/ SFMT/ FSI / SCO/ SDO/ DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8
GENERAL DESCRIPTION
The AD7723 is a complete 16-bit, sigma-delta ADC. The part operates from a +5 V supply. The analog input is continuously sampled, eliminating the need for an external sample-and-hold. The modulator output is processed by a finite impulse response (FIR) digital filter. The on-chip filtering combined with a high oversampling ratio reduces the external antialias requirements to first order in most cases. The digital filter frequency response can be programmed to be either low pass or band pass. The AD7723 provides 16-bit performance for input bandwidths up to 460 kHz at an output word rate up to 1.2 MHz. The sample rate, filter corner frequencies and output word rate are set by the crystal oscillator or external clock frequency. Data can be read from the device in either serial or parallel format. A stereo mode allows data from two devices to share a single serial data line. All interface modes offer easy, high speed connections to modern digital signal processors.
The part provides an on-chip 2.5 V reference. Alternatively, an external reference can be used. A power-down mode reduces the idle power consumption to 200 µW. The AD7723 is available in a 44-lead PQFP package and is specified over the industrial temperature range from 40°C to +85°C. Two input modes are provided, allowing both unipolar and bipolar input ranges.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998
AD7723SPECIFICATIONS1 f
Parameter
DYNAMIC SPECIFICATIONS2, 3 Decimate by 32 Bipolar Mode Signal to Noise Full Power Half Power Total Harmonic Distortion4 Spurious Free Dynamic Range4 Unipolar Mode Signal to Noise Total Harmonic Distortion4 Spurious Free Dynamic Range4 Bandpass Filter Mode Bipolar Mode Signal to Noise Decimate by 16 Bipolar Mode Signal to Noise
(AVDD = DVDD = +5 V 5%; AGND = AGND1 = AGND2 = DGND = 0 V; CLKIN = 19.2 MHz; REF2 = 2.5 V; TA = TMIN to TMAX ; unless otherwise noted)
Min B Version Typ Max Units
Test Conditions/Comments
HALF_PWR = 0 or 1 fCLKIN = 10 MHz When HALF-PWR = 1
2.5 V Reference 3 V Reference
87 88.5 86.5
90 91 89 96
2.5 V Reference 3 V Reference 87 89 90
90 92 90
dB dB dB dB dB dB dB dB dB
76
79
dB
Signal to Noise Total Harmonic Distortion4 Spurious Free Dynamic Range4 Unipolar Mode Signal to Noise Signal to Noise Total Harmonic Distortion4
Measurement Bandwidth = 0.383 × FO 2.5 V Reference 3 V Reference Measurement Bandwidth = 0.5 × FO 2.5 V Reference 3 V Reference 2.5 V Reference 3 V Reference Measurement Bandwidth = 0.383 × FO Measurement Bandwidth = 0.5 × FO
82 83 78
86 87 81.5 88 86 90 88 84 81 89
dB dB dB dB dB dB dB dB dB dB
DIGITAL FILTER RESPONSE Low Pass Decimate by 32 0 kHz to fCLKIN /83.5 fCLKIN /66.9 fCLKIN /64 fCLKIN /51.9 to fCLKI N/2 Group Delay Settling Time Low Pass Decimate by 16 0 kHz to fCLKIN/41.75 fCLKIN /33.45 fCLKIN /32 fCLKIN /25.95 to fCLKIN /2 Group Delay Settling Time Band Pass Decimate by 32 fCLKIN /51.90 to fCLKIN /41.75 fCLKIN /62.95, fCLKI N/33.34 fCLKIN /64, fCLKIN /32 0 kHz to fCLKIN /83.5, fCLKIN /25.95 to fCLKIN /2 Group Delay Settling Time Output Data Rate, FO Decimate by 32 Decimate by 16 ANALOG INPUTS Full-Scale Input Span Bipolar Mode Unipolar Mode VIN(+) VIN()
± 0.001 3 6 90 1 2 9 3 / 2 fCLKIN 1 2 9 3 / fC L K I N ± 0.001 3 6 90 5 4 1 / 2 fC L K I N 541/fCLKIN ± 0.001 3 6 90 1 2 9 3 / 2 fCLKIN 1 2 9 3 / fC L K I N fC L K I N / 3 2 fC L K I N / 1 6
dB dB dB dB
dB dB dB dB
dB dB dB dB
0
± 4 / 5 × V REF2 8 / 5 × V REF2
V V
2
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AD7723
Parameter
ANALOG INPUTS (Continued) Absolute Input Voltage Input Sampling Capacitance Input Sampling Rate, fCLKIN CLOCK CLKIN Duty Ratio REFERENCE REF1 Output Resistance Using Internal Reference REF2 Output Voltage REF2 Output Voltage Drift Using External Reference REF2 Input Impedance REF2 External Voltage Range STATIC PERFORMANCE Resolution Differential Nonlinearity Integral Nonlinearity DC CMRR Offset Error Gain Error 5 LOGIC INPUTS (Excluding CLKIN) VINH, Input High Voltage VINL, Input Low Voltage CLOCK INPUT (CLKIN) VINH, Input High Voltage VINL, Input Low Voltage ALL LOGIC INPUTS IIN, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES AVDD IAVDD DVDD IDVDD Power Consumption6 VIN = 0 V to DVDD
Test Conditions/Comments
VIN(+) and/or VIN()
Min
AGND
B Version Typ
Max
AVDD
Units
V pF MHz % k
2 19.2 45 3 2.39 2.54 60 4 2.5 2.69 55
V ppm/°C k V Bits LSB LSB dB mV % FSR V V V V µA pF V V V mA mA V mA mA µW
REF1 = AGND 1.2 16 Guaranteed Monotonic
3.15
± 0.5 ±2 80 ± 20 ± 0.5 2.0
±1
0.8 3.8 0.4 ± 10 10 4.0 0.4 4.75 HALF_PWR = Logic Low HALF_PWR = Logic High 4.75 HALF_PWR = Logic Low HALF_PWR = Logic High Standby Mode 25 15 50 25 5.25 60 33 5.25 35 20 200
|IOUT| = 200 µA |IOUT| = 1.6 mA
NOTES 1Operating temperature range is as follows: B Version: 40°C to +85°C. 2Typical values for SNR apply for parts soldered directly to a printed circuit board ground plane. 3Dynamic specifications apply for input signal frequencies from dc to 0.0240 × f CLKIN in decimate by 16 mode and from dc to 0.0120 × f CLKIN in decimate by 32 mode. 4When using the internal reference, THD and SFDR specifications apply only to input signals above 10 kHz with a 10 µF decoupling capacitor between REF2 and AGND2. At frequencies below 10 kHz, THD degrades to 84 dB and SFDR degrades to 86 dB. 5Gain Error excludes Reference Error. 6CLKIN and digital inputs static and equal to 0 or DV DD. Specifications subject to change without notice.
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AD7723 TIMING SPECIFICATIONS
Parameter CLKIN Frequency CLKIN Period (tCLK = 1/fCLK) CLKIN Low Pulsewidth CLKIN High Pulsewidth CLKIN Rise Time CLKIN Fall Time FSI Setup Time FSI Hold Time FSI High Time1 CLKIN to SCO Delay SCO Period2, SCR = 1 SCO Period2, SCR = 0 SCO Transition to FSO High Delay SCO Transition to FSO Low Delay SCO Transition to SDO Valid Delay SCO Transition from FSI3 SDO Enable Delay Time SDO Disable Delay Time DRDY High Time2 Conversion Time2 (Refer to Tables I and II) CLKIN to DRDY Transition CLKIN to DATA Valid CS/RD Setup Time to CLKIN CS/RD Hold Time to CLKIN Data Access Time Bus Relinquish Time SYNC Input Pulsewidth SYNC Low Time before CLKIN Rising DRDY High Delay after Rising SYNC DRDY Low Delay after SYNC Low
NOTES 1FSO pulses are gated by the release of FSI (going low). 2Guaranteed by design. 3Frame Sync is initiated on the falling edge of CLKIN. Specifications subject to change without notice.
(AVDD = DVDD = +5 V 5%; AGND = AGND1 = DGND = 0 V; fCLKIN = 19.2 MHz; CL = 50 pF; SFMT = Logic Low or High, CFMT = Logic Low or High; TA = TMIN to TMAX unless otherwise noted)
Symbol F CLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t10 t11 t12 t13 t14 t15 t1 6 t17 t18 t1 9 t2 0 t2 1 t2 2 t23 t2 4 t2 5 t26 t2 7 t2 8 Min 1 0.052 0.45 × t1 0.45 × t1 5 5 0 0 25 2 1 0 0 5 60 5 5 2 16/32 35 20 0 20 20 20 1 0 25 35 2049 35 35 50 35 Typ Max 19.2 1 0.55 × t1 0.55 × t1 Units MHz µs ns ns 5 5 1 40 ns ns tCLK ns tCLK tCLK ns ns ns ns ns tCLK tCLK ns ns ns ns ns ns tCLK ns ns tCLK
5 5 12 t C L K + t2 20 20
IOL 1.6mA TO OUTPUT PIN
+1.6V CL 50pF IOH 200 A
Figure 1. Load Circuit for Timing Specifications
4
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AD7723
t5
CLKIN 2.3V 0.8V
t4
t2 t3
t1 t6
FSI
t7
t8 t9
SCO
t9 t10
Figure 2. Serial Mode Timing for Clock Input, Frame Sync Input and Serial Clock Output
32 CLKIN CYCLES CLKIN
t8
FSI (SFMT = 1)
t14
SCO (CFMT = 0)
t11
FSO (SFMT = 0)
t12
FSO (SFMT = 1)
t11
t13
SDO D15 D14 D13 D2 D1 D0 D15 D14
Figure 3. Serial Mode 1. Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output and Serial Data Output (Refer to Table I for Control Inputs, TSI = DOE)
32 CLKIN CYCLES
CLKIN
t8
FSI
t14
SCO (CFMT = 0)
t11
FSO
t12
t13
SDO D2 D1 D0 D15 D14 D13 D12 D11 D5 D4 D3 D2 D1 D0 D15 D14
Figure 4. Serial Mode 2. Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output and Serial Data Output (Refer to Table I for Control Inputs, TSI = DOE)
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