|
Details, datasheet, quote on part number:AD7724AST
| |
| Part: | AD7724AST |
| Category: | Data Conversion => ADC (Analog to Digital Converters) => >14 bit => 16 bit |
| Description: | Dual, 7th-Order, Sigma-delta Modulator |
| Company: | Analog Devices |
| Datasheet: | Download AD7724AST datasheet File size : 295 kB |
| Request For quote: | Find where to buy AD7724AST
|
| |
Datasheet text preview:
a
FEATURES 13 MHz Master Clock Frequency 0 V to +2.5 V or 1.25 V Input Range Single Bit Output Stream 90 dB Dynamic Range Power Supplies AVDD, DVDD: 5 V 5% DVDD1: 3 V 5% Logic Outputs 3 V/5 V Compatible On-Chip 2.5 V Voltage Reference 48-Lead LQFP
Dual CMOS - Modulators AD7724
FUNCTIONAL BLOCK DIAGRAM
REF1 REF2A 2.5V REFERENCE REF2B
AD7724
AVIN(+) AVIN()
MODULATOR A
-
ADATA
SCLK BVIN(+) BVIN()
MODULATOR B
-
BDATA XTAL OFF CLOCK CIRCUITRY XTAL1 XTAL2/MCLK DVAL
MZERO GC BIP STBY RESET CONTROL LOGIC
DVDD
DVDD1
DGND
AVDD
AGND
GENERAL DESCRIPTION
This device consists of two seventh order sigma-delta modulators. Each modulator converts its analog input signal into a high speed 1-bit data stream. The part operates from a 5 V power supply and accepts a differential input range of 0 V to +2.5 V or ± 1.25 V centered about a common-mode bias. The analog inputs are continuously sampled by the analog modulators, eliminating the need for external sample-and-hold circuitry. The input information is contained in the output stream as a density of ones. The original information can be digitally reconstructed with an appropriate digital filter. The part provides an accurate on-chip 2.5 V reference for each modulator. A reference input/output function is provided to allow either the internal reference or an external system reference to be used as the reference source for the modulator. The device is offered in a 48-lead LQFP package and designed to operate from 40°C to +85°C.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002
AD=77MHz4SPEsineIwave,CATIONS=12(.A5VV;DT==5TV 2 ac-coupled C FI REF2A = REF2B D f 13
MCLK
A
MIN
5%; DVDD = 5 V 5%, DVDD1 = 3 V to TMAX, unless otherwise noted.)
5%; AGND = DGND = 0 V,
Parameter STATIC PERFORMANCE Integral Nonlinearity Offset Error Gain Error2 Offset Error Drift Gain Error Drift Unipolar Mode Bipolar Mode ANALOG INPUTS Signal Input Span (VIN(+) VIN()) Bipolar Mode Unipolar Mode Maximum Input Voltage Minimum Input Voltage Input Sampling Capacitance Input Sampling Rate Differential Input Impedance REFERENCE INPUTS REF1 Output Voltage REF1 Output Voltage Drift REF1 Output Impedance Reference Buffer Offset Voltage Using Internal Reference REF2 Output Voltage REF2 Output Voltage Drift Using External Reference REF2 Input Impedance External Reference Voltage Range DYNAMIC SPECIFICATIONS Bipolar Mode
3
A Version ± 0.003 ± 0.24 ± 0.6 ± 37.69 ± 37.69 ± 18.85
Unit % FSR typ % FSR typ % FSR typ µV/°C typ
Test Conditions/Comments When Tested with Ideal FIR Filter as in Figure 1
REF2 Is an Ideal Reference, REF1 = AGND µV/°C typ µV/°C typ
± VREF2/2 0 to VREF2 AVDD 0 2 2 f MCLK 109/(8 fMCLK) 2.32 to 2.68 60 4 ± 12 2.32 to 2.68 60 109/(16 fMCLK) 2.32 to 2.68
V max V max V V pF typ MHz k typ V min/max ppm/°C typ k typ mV max V min/max ppm/°C typ
B I P = VIH B I P = VIL
Offset Between REF1 and REF2
REF1 = AGND k typ V min/max Applied to REF1 or REF2 When Tested with Ideal FIR Filter as in Figure 1 BIP = VIH, VCM = 2.5 V, VIN(+) = VIN() = 1.25 V p-p or VIN() = 1.25 V, VIN(+) = 0 V to 2.5 V Input BW = 0 kHz94.25 kHz Input BW = 0 kHz94.25 kHz Input BW = 0 kHz94.25 kHz BIP = VIL, VIN() = 0 V, VIN(+) = 0 V to 2.5 V Input BW = 0 kHz94.25 kHz Input BW = 0 kHz101.556 kHz Input BW = 0 kHz101.556 kHz VIN(+) = VIN() = 2.5 V p-p, VCM = 1.25 V to 3.75 V, 20 kHz
Signal-to-(Noise + Distortion) Total Harmonic Distortion Spurious Free Dynamic Range Unipolar Mode Signal-to-(Noise + Distortion) Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion AC CMRR CLOCK Square Wave4 MCLK Duty Ratio VMCLKH, MCLK High Voltage VMCLKL, MCLK Low Voltage Sine Wave XTAL1 Voltage Swing LOGIC INPUTS VIH, Input High Voltage VIL, Input Low Voltage IINH, Input Current CIN, Input Capacitance
90 86 90 90 88 90 90 93 96
dB typ dB min dB max dB max dB typ dB typ dB typ dB typ dB typ
45 to 55 4 0.4 0.4 4 2.4 0.8 10 10
% max V min V max V p-p min V p-p max V min V max µA max pF max
For Specified Operation MCLK Uses CMOS Logic
XTAL_OFF Tied Low
2
REV. B
AD7724
Parameter LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES AVDD/DVDD DVDD1 IDD (Total for AVDD, DVDD) Active Mode Standby Mode A Version DVDD1 0.2 0.4 4.75/5.25 2.85/5.25 60 20 Unit V min V max V min/V max V min/V max Digital Inputs Equal to 0 V or DVDD mA max µA max Test Conditions/Comments |IOUT| 200 µA |IOUT| 1.6 mA
NOTES 1 Operating temperature range is as follows: A Version: 40°C to +85°C. 2 Gain Error excludes reference error. The modulator gain is calibrated wrt the voltage on the REF2 pin. 3 Measurement Bandwidth = 0.5 × fMCLK; Input Level = 0.05 dB. 4 When a square wave clock is used, the dynamic specifications will degrade by 1 dB typically. Specifications subject to change without notice.
BIT STREAM
94.25kHz 120dB DECIMATE BY 32
94.25kHz 90dB DECIMATE BY 2 16-BIT OUTPUT
FILTER 1
304.687kHz
FILTER 2
108.874kHz
BANDWIDTH = 94.25kHz TRANSITION = 304.687kHz ATTENUATION = 120dB COEFFICIENTS = 384
BANDWIDTH = 94.25kHz TRANSITION = 108.874kHz ATTENUATION = 90dB COEFFICIENTS = 151
Figure 1. Digital Filter (Consists of Two FIR Filters). This Filter is Implemented on the AD7722.
REV. B
3
AD7724 TIMING CHARACTERISTICS1, 2
Parameter fM C L K tDELAY t1 t2 t3 t4 t5 t6 t7 t8 t9 100 15 14 67 0.45 × tMCLK 0.45 × tMCLK 15 10 10 2 0 × t MCLK 3 t3t8
(AVDD = 5 V 5%; DVDD = 5 V 5%; DVDD1 = 3 V REF2B = 2.5 V, unless otherwise noted.)
Unit kHz min MHz max ns max ns min ns min ns min ns min ns min ns min ns max ns max ns max
5%; AGND = DGND = 0 V, REF2A =
Limit at TMIN, TMAX (A Version)
Conditions/Comments Master Clock Frequency 13 MHz for Specified Performance MCLK to SCLK Delay Master Clock Period Master Clock Input High Time Master Clock Input Low Time Data Hold Time After SCLK Rising Edge RESET Pulsewidth RESET Low Time Before MCLK Rising DVAL High Delay After RESET Low Data Access Time After SCLK Falling Edge Data Valid Time Before SCLK Rising Edge
NOTES 1 Sample tested at 25°C to ensure compliance. 2 Guaranteed by design.
IOL 1.6mA TO OUTPUT PIN
1.6V CL 50pF IOH 200 A
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
t1 t2 t3 t8
DATA (O)
SCLK (O)
t4
t9
NOTE: O SIGNIFIES AN OUTPUT
Figure 3. Data Timing
MCLK (I)
t6
RESET (I)
t5 t7
DVAL (O)
NOTE: I SIGNIFIES AN INPUT O SIGNIFIES AN OUTPUT
Figure 4. RESET Timing
4
REV. B
AD7724
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
PIN CONFIGURATION
AGND REF2A AGND REF1 AVDD NC REF2B AGND
XTAL1/MCLK DVDD
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . 1 V to +1 V AGND to DGND . . . . . . . . . . . . . . . . . . . . 0.3 V to +0.3 V Digital Inputs to DGND . . . . . . . . 0.3 V to DVDD + 0.3 V Digital Outputs to DGND . . . . . . . 0.3 V to DVDD + 0.3 V VIN(+), VIN() to AGND . . . . . . . 0.3 V to AVDD + 0.3 V REF1 to AGND . . . . . . . . . . . . . . . 0.3 V to AVDD + 0.3 V REF2 to AGND . . . . . . . . . . . . . . . 0.3 V to AVDD + 0.3 V REFIN to AGND . . . . . . . . . . . . . . 0.3 V to AVDD + 0.3 V Operating Temperature Range . . . . . . . . . . . 40°C to +85°C Storage Temperature Range . . . . . . . . . . . . 65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 75°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
NC
NC
48 47 46 45 44 43 42 41 40 39 38 37
AVDD AGND 2 AVIN() 3 NC 4 AVIN(+) 5 AGND 6 AVDD 7 NC 8 STBY 9 MZERO 10 RESET 11 NC 12
1
NC NC
36 AVDD 35 AGND 34 BVIN() 33 NC 32 BVIN(+) 31 AGND 30 AVDD 29 NC 28 GC 27 BIP 26 XTAL_OFF 25 NC
PIN 1 IDENTIFIER
AD7724
TOP VIEW (Not to Scale)
13 14 15 16 17 18 19 20 21 22 23 24
XTAL1
NC
SCLK DVDD1
DGND DGND
NC = NO CONNECT
ORDERING GUIDE
Model AD7724AST
Temperature Range 40°C to +85°C
Package Description 48-Lead Plastic Thin Quad Flatpack (LQFP)
ADATA BDATA
Package Option ST-48
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7724 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
5
DVAL
NC
|
|
