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Details, datasheet, quote on part number:AD7725BS
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| Part: | AD7725BS |
| Category: | Data Conversion => ADC (Analog to Digital Converters) => >14 bit |
| Description: | Programmable High-Speed, Sigma-delta ADC |
| Company: | Analog Devices |
| Datasheet: | Download AD7725BS datasheet File size : 244 kB |
| Request For quote: | Find where to buy AD7725BS
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Datasheet text preview:
PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES P r o g r a m m a b l e Filtering: A n y characteristic up to 108 tap FIR and/or IIR P o l y n o m i a l Signal Conditioning up to 8th Order P r o g r a m m a b l e Decimation and Output Word Rate F l e x i b l e Programming Modes P a r a l l e l / S e r i a l Interface B o o t from ROM (BFR) - Internal Default Filter B o o t from DSP or External EPROM 1 9 . 2 MHz Max Master Clock Frequency 0 to +4V (Single Ended) or ±2V (Differential) Input Range P o w e r Supplies: AV D D, DV DD : +5V ± 5% O n - C h i p 2.5V Voltage Reference 4 4 - P i n PQFP Package T Y P I C A L APPLICATIONS Radar Sonar A u x i l l a r y Car Functions M e d i c a l Communications
16-Bit Sigma-Delta ADC with Programmable Post Processor AD7725
F U N C T I O N A L BLOCK DIAGRAM
RE F2 REF 1 AVDD AG ND V IN(+ ) VI N(-) PRE SET FI LT ER Po st P ro cessor Defau lt F ilt er (RO M) X TAL CL O CK DV DD DGND
A D7725
2. 5V RE FE RENCE
MO D
UN I HAL F_P WR S TBY SYNC S/P RD/W R SOE / CS CF MT /RS D V AL /INT SDI/ DB0
X TAL _O FF XTAL CLK IN SMO DE1/ DB15 SM ODE 0/DB14 SCR/ DB13 CF G END/D B12 DB11 DB10 F S0/ DB9
CO NT ROL L O GI C
RE SE TCF G/ DB4 I NIT /DB5
ERR/ DB1
G E N E R A L DESCRIPTION
The AD7725 is a complete 16-bit, sigma-delta analog to digital converter with on chip user-programmable signal conditioning. The output of the modulator is processed by three cascaded finite impulse response (FIR) filters. This is followed by a user-programmable post processor. The user has complete control over the filter response (lowpass, highpass, bandpass, stopband), the filter coefficients and the decimation ratio. The post processor accepts up to 108 coefficients. The AD7725 provides 16-bit performance for input bandwidths up to 460 kHz and an output word rate of 1.2 MHz maximum. The input sample rate is set either by the crystal oscillator or an external clock. The output is available via a serial or parallel interface. The device contains a post processor which permits the signal conditioning characteristics to be programmed through the parallel microprocessor interface, through a serial interface or, it may boot at power-on-reset from its default filter (internal ROM) or from an external serial EPROM.
The post processor is a fully programmable core which provides processing power of up to 130 million accumulates (MAC) per second. To program the post processor, either the on-board default filter or a user defined filter in the form of a configuration file can be loaded. The configuration file can be generated by a digital filter design package called 'Filter Wizard' which is available from Systolix (www.systolix.co.uk). This package allows the user to design different filter types and generates the appropriate configuration file to be downloaded to the postprocessor. This part provides an accurate on-chip 2.5 V reference for the modulator. A reference input/output function is provided to allow either the internal reference or an external system reference to be used as the reference source for the modulator. The device is offered in a 44-pin PQFP package and is designed to operate from -40oC to +85oC.
R e v PrL 4/03/02
Information furnished by Analog Devices is believed to be accurate a n d reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002
SCO / DB7
S DO/ DB8
F SI /DB6
DB2 DB3
PRELIMINARY TECHNICAL DATA
AD7725
SPECIFICATIONS1
Parameter D Y N A M I C SPECIFICATIONS 2 P R E S E T FILTER OUTPUT N o i s e Analysis Noise relative to a Carrier RMS noise (fs/4 to 3fs/8) RMS noise (3fs/8 to fs/2) T o t a l Harmonic Distortion 3,4 Spurious Free Dynamic Range 3,4 D E F A U L T FILTER B i p o l a r Mode Signal to Noise 4
(AVDD = +5V ± 5%; AGND = AGND1= AGND2 = DGND = 0V; FCLKIN = 19.2 MHz; REF2 = 2.5 V; TA = TMIN to TMAX; unless otherwise noted)
Test Conditions/Comments HALF_PWR = 0 or 1 fCLKIN = 9.6MHz when HALF_PWR = 1 FIN = 10kHz See Figure 1 0 to fs/4 Serial Parallel Serial Parallel Min B Version Typ Max Units
-135 79 84 78 79
-132
-88 -90 Internal ROM FIR Filter = 0.383 x FO = 0.5 x FO 82 83 78 86 87 81.5 -88 -86 -90 -88 = 0.383 x FO = 0.5 x FO 84 81 -89
dBc/Hz dB dB dB dB dB dB
Measurement Bandwidth 2.5V Reference 3V Reference Signal to Noise 4 Measurement Bandwidth T o t a l Harmonic Distortion 3,4 2.5V Reference 3V Reference Spurious Free Dynamic Range 3,4 2.5V Reference 3V Reference U n i p o l a r Mode Signal to Noise 3,4 Measurement Bandwidth Signal to Noise 3,4 Measurement Bandwidth T o t a l Harmonic Distortion 3
dB dB dB dB dB dB dB dB dB dB
A N A L O G INPUTS Full Scale Input Span B i p o l a r Mode U n i p o l a r Mode Absolute Input Voltage I n p u t Sampling Capacitance Input Sampling Rate, FCLKIN CLOCK CLKIN Duty Ratio REFERENCE R REF1 Output Resistance e f e r e n c e Buffer O f f s e t Voltage Using Internal Reference REF2 Output Voltage REF2 Output Voltage Drift U s i n g External Reference REF2 Input Impedance R E F 2 External Voltage Range S T A T I C PERFORMANCE Resolution D i f f e r e n t i a l Nonlinearity (DNL) 4 I n t e g r a l Nonlinearity (INL) 4 D C CMRR 4 O f f s e t Error B i p o l a r Mode 4 U n i p o l a r Mode 4 Gain Error4,5
VI N ( + ) - V I N ( - ) Differential or Single Ended Input Single Ended Input VIN(+) and/or VIN(-)
±4/5xVREF2 0 A GND 2
V 8/5xVREF2 V AVDD V pF 19.2 MHz 55 % k mV 2.69 V ppm/°C k V Bits LSB LSB dB mV mV %FSR
45 3 Offset between REF1 and REF2 2.39 ±10 2.54 60 4 2.5
REF1 = AGND 1.2 16* * G u a r a n t e e d Monotonic 80 Differential or Single Ended i/p Single Ended i/p
3.15
±0.5 ±2
±1*
±5 ±25 ±0.5
2
Rev PrL
PRELIMINARY TECHNICAL DATA
AD7725
SPECIFICATIONS1
Parameter L O G I C INPUTS (Excluding CLKIN) VINH, Input High Voltage VINL, Input Low Voltage C L O C K INPUT (CLKIN) VINH, Input High Voltage VINL, Input Low Voltage A L L LOGIC INPUTS IIN, Input Current CIN, Input Capacitance L O G I C OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage P O W E R SUPPLIES AVDD IAVDD D VDD IDVDD P o w e r Consumption 6
(AVDD = +5V ± 5%; AGND= AGND1= AGND2 = DGND = 0V; FCLKIN = 19.2 MHz; REF2 = 2.5 V; TA = TMIN to TMAX; unless otherwise noted)
Test Conditions/Comments Min Typ Max Units
2.0 0.8 3.8 0.4 VIN = 0 V to DVDD ± 10 10 4.0 0.4 4.75 H A L F _ P W R = Logic Low H A L F _ P W R = Logic High 4.75 H A L F _ P W R = Logic Low H A L F _ P W R = Logic High Standby Mode 20 15 50 25 5.25 60 TBD 5.25 75 TBD 200
V V V V µA pF V V V mA mA V mA mA µW
|IOUT| = 200 mA |IOUT| = 1.6 mA
NOTES 1 O p e r a t i n g Temperature Range is as follows: B Version: -40°C to +85°C 2 M e a s u r e m e n t Bandwidth = 0.5*F O 3 W h e n using the internal reference, THD and SFDR specifications apply only to input signals above 10kHz with a 10µF decoupling capacitor b e t w e e n REF2 and AGND2. At frequencies below 10kHz, THD degrades to 84 dB and SFDR degrades to 86dB. 4 See 'Terminology' Section 5 G a i n Error excludes Reference Error 6 CLKIN and digital inputs static and equal to 0 or DV DD S p e c i f i c a t i o n s subject to change without notice
Rev PrL
3
PRELIMINARY TECHNICAL DATA
AD7725
Preset Filter, Default Filter and Post Processor Characteristics1
Parameter D I G I T A L FILTER RESPONSE P R E S E T FIR Data Output Rate StopBand Attenuation LowPass Corner Frequency G r o u p Delay S e t t l i n g Time D E F A U L T FILTER 0 kHz to FCLKIN/234.1 F C L K I N/ 1 7 9 . 4 F C L K I N/ 1 6 5 . 5 FCLKIN/128 to FCLKIN/2 G r o u p Delay S e t t l i n g Time Output Data Rate, F O Internal ROM FIR Filter ± 0.001 -3 -6 -120 TBD TBD F CLKIN/ 3 2 MCLK/8 24 30 2 1 MCLK/256 108 256 5 MCLK/16 Bits Bits dB dB dB dB Test Conditions/Comments Min Typ Max Units MCLK/8 70 MCLK/16 1 3 3 / 2 x F CLKIN 1 3 3 / F CLKIN dB
P O S T PROCESSOR CHARACTERISTICS Input Data Rate C o e f f i c i e n t Precision A r i t h m e t i c Precision No. of Taps Permitted D e c i m a t i o n Factor No. of Decimation Stages Output Data Rate
NOTES 1 T h e s e characteristics are fixed by the design.
4
Rev PrL
PRELIMINARY TECHNICAL DATA
AD7725
TIMING SPECIFICATIONS
Parameter C L K I N Frequency CLKIN Period (tCLK = 1/fCLK) CLKIN Low Pulsewidth C L K I N High Pulsewidth CLKIN Rise Time C L K I N Fall Time CLKIN to SCO Delay SCO Period: SCR = 0 SCR = 1 Serial Interface (DSP Mode Only) FSI FSI SDI SDI Setup Time Before SCO Transition Hold Time After SCO Transition Setup Time Hold Time t8 t9 t10 t1 1 t1 2 t13 t1 4 t1 5 t16 t1 7 t18 t19 fCLK t1 t2 t3 t4 t5 t6 t7 t7
(AVDD = +5 V ± 5%; DVDD = +5 V ± 5%; AGND = DGND = 0 V, REF2 = +2.5 V unless otherwise noted)
Symbol Min 1 0.05 0 . 4 5 x t1 0 . 4 5 x t1 5 5 25 1 2 20 0 20 0 5 5 5 5 10 10 10 10 8 8 20 10 Typ Max 20 1 0 . 5 5 x t1 0 . 5 5 x t1 40 Units MHz µs
ns ns ns tCLK tCLK ns ns ns ns ns ns ns ns tCLK tCLK tCLK ns
Serial Interface (DSP and BFR Modes) SCO Transition to FSO High Delay SCO Transition to FSO Low Delay SDO Setup Before SCO Transition SDO Hold After SCO Transition Serial Interface (EPROM Mode) SCO SCO SOE Data High Time Low Time Low to First SCO Rising Edge Setup Before SCO Rising Edge
Parallel Interface Data Write RS Low to CS Low WR Setup Before CS Low RS Hold After CS Rising Edge CS Pulse Width WR Hold After CS Rising Edge Data Setup time Data Hold Time Data Read RS Low to CS Low RD Setup Before CS Low RS Hold After CS Rising Edge RD Hold After CS Rising Edge D a t a Valid After CS Falling Edge Data Hold After CS Rising Edge Status Read/Instruction Write CS Duty Cycle Interrupt Clear After CS Low RD Setup to CS Low RD Hold After CS Rising Edge Read Data Access Time Read Data Hold After CS Rising Edge Write Data Setup Before CS Rising Edge Write Data Hold After CS Rising Edge
NOTE G u a r a n t e e d by design.
t2 0 t2 1 t22 t23 t2 4 t2 5 t2 6 t2 7 t2 8 t29 t30 t3 1 t3 2 t33 t3 4 t3 5 t36 t37 t3 8 t3 9 t40
10 10 10 50 10 10 0 10 10 10 10 25 5 1 5 10 10 25 10 10 5
ns ns ns ns ns ns ns ns ns ns ns ns ns tCLK ns ns ns ns ns ns ns
Rev PrL
5
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