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Details, datasheet, quote on part number:AD7729
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| Part: | AD7729 |
| Category: | Data Conversion => ADC (Analog to Digital Converters) => >14 bit |
| Description: | 3 V, Dual Sigma-delta ADC With Auxiliary DAC |
| Company: | Analog Devices |
| Datasheet: | Download AD7729 datasheet File size : 145 kB |
| Request For quote: | Find where to buy AD7729
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Datasheet text preview:
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FEATURES +3 V Supply Voltage Baseband Serial Port (BSPORT) Differential IRx and QRx ADC Channels Two 15-Bit Sigma-Delta A/D Converters FIR Digital Filters 64 dB SNR Output Word Rate 270.83 kHz Twos Complement Coding On-Chip Offset Calibration Power-Down Mode Auxiliary D/A Converter Auxiliary Serial Port (ASPORT) On-Chip Voltage Reference Low Power 28-Lead TSSOP/28-Lead SOIC APPLICATIONS GSM Basestations Pagers FUNCTIONAL BLOCK DIAGRAM
DVDD2 DVDD1 DGND AGND AVDD1
Dual Sigma-Delta ADC with Auxiliary DAC AD7729
GENERAL DESCRIPTION
This monolithic 3 V CMOS device is a low power, two-channel, input port with signal conditioning. The receive path is composed of two high performance sigma-delta ADCs with digital filtering. A common bandgap reference feeds the ADCs. A control DAC is included for such functions as AFC. The auxiliary functions can be accessed via the auxiliary port (ASPORT). This device is available in a 28-lead TSSOP package or a 28-lead SOIC package.
AVDD2
ASDI ASDIFS ASCLK ASDO ASDOFS ASE AUXILIARY SERIAL INTERFACE 10-BIT AUXDAC AUXDAC
BSDI BSDIFS BSCLK BSDO BSDOFS BSE BASEBAND SERIAL INTERFACE
OFFSET ADJUST
DECIMATION FIR DIGITAL FILTER
M ODULATOR
IRxP IRxN
OFFSET ADJUST
DECIMATION FIR DIGITAL FILTER
M ODULATOR
QRxP QRxN
DIVIDE BY 2 MCLK RxON RESETB MUX REFERENCE REFCAP REFOUT
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998
V 10%; DVDD1 = DVDD2 AVD7=713 MHz; RxPOWER1 =I0; RxPOWER0IO1;NMCLKDIVAV=D0;1T==AVDD2to=T+3 unless otherwise noted) = +3 V 29SPEC FICAT = S1 ( D T 0 ,f
CLK A MIN MAX
10%; DGND = AGND =
Parameter REFERENCE REFCAP Absolute Voltage, VREFCAP REFCAP TC REFOUT Absolute Voltage, VREFOUT REFOUT TC ADC CHANNEL SPECIFICATIONS Resolution ADC Signal Range V BIAS Differential Signal Range Single-Ended Signal Range Input Sample Rate Output Word Rate DC Accuracy Precalibration Offset Error Post Calibration Offset Error Post Calibration Offset Error TC Input Resistance (DC) Input Capacitance Dynamic Specifications Dynamic Range Signal to (Noise + Distortion) Gain Error Gain Match Between Channels Filter Settling Time Frequency Response 0 kH z 70 kHz 85 kHz 96 kHz 135 kHz >170 kHz Absolute Group Delay Group Delay Between Channels (0 kHz96 kHz) Coding AUXILIARY CONVERTER2 Resolution Output Range Code 000 Offset Error Code 3FF Gain Error DC Accuracy Integral Nonlinearity Differential Nonlinearity Update Rate Load Resistance Load Capacitance I SINK Full-Scale Settling Time LSB Settling Time Coding
AD7729A
Units
Test Conditions/Comments
1.3 ± 5% 50 1.3 ± 10% 50 15 2 VREFCAP VREFCAP/2 to (AVDD VREFCAP /2) VREFCAP to (AVDD VREFCAP ) VBIAS ± V REFCAP/2 V BIAS ± V REFCAP 13 270.83 ± 45 ± 10 50 1.23 10 67 64 ±1 ± 0.5 ± 0.2 47 ± 0.05 1 3.0 55 55 23 5 Twos Complement
V min/max ppm/°C typ V min/max ppm/°C typ Bits V p-p Volts Volts V min/max V min/max MSPS kHz mV typ mV max µV/°C typ M typ pF typ dB typ dB min dB max dB max dB max µs typ dB max/min dB max dB max dB max dB max µs typ ns typ
0.1 µF Capacitor Required from REFCAP to AGND
0.1 µF Capacitor Required from REFOUT to AGND RxON = 1
Differential Single-Ended For Both Positive and Negative Analog Inputs For Positive Analog Inputs; Negative Analog Inputs = VBIAS
TC = Temperature Coefficient
Input Frequency = 67.7 kHz
Input Frequency = 67.7 kHz, wrt 1.3 V Input Frequency = 67.7 kHz, wrt VREFCAP
Does Not Include Input Antialias RC Circuit
10 2/32 × VREFCAP ± 35 2 VREFCAP 60 +100
Bits V mV max V mV min mV max Maximum Output for Specified Accuracy = AVDD 0.2 V or 2.6 V, Whichever Is Lower
±4 ±2 540 10 50 50 4 2 Binary
LSB max LSB max kHz max k min pF max µA typ µs typ µs typ
Guaranteed Monotonic to 9 Bits See Figure 1 See Figure 1
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AD7729
Parameter LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IIH, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage IOZL, Low Level Output Three-State Leakage Current IOZH, High Level Output Three-State Leakage Current POWER SUPPLIES AVDD1, AVDD2 DVDD1, DVDD2 I DD AD7729A Units Test Conditions/Comments VDD 0.8 0.8 10 10 VDD 0.4 0.4 10 10 V min V max µA max pF max V min V max µA max µA max V min/max V min/max See Table I |IOUT| < 100 µA |IOUT| < 100 µA
2.7/3.3 2.7/3.3
NOTES 1 Operating Temperature Range: 40°C to +105°C. Therefore, T MIN = 40°C and TMAX = +105°C. 2 During power-down, the AUXDAC has an output resistance of 30 k approximately to AGND. Specifications subject to change without notice.
50CF p
L
RL 10k
Figure 1. AUXDAC Load Equivalent Circuit
Table I. Current Summary (AVDD1 = AVDD2 = DVDD1 = DVDD2 = +3.3 V, RxPOWER1 = 0, RxPOWER0 = 1)
Internal Analog Digital Current Current (typ) (typ) 4.2 2 0.7 1 0.0001 0.0001 3.4 0.86 0.0001 0.0001 0.04 0.0001 External Interface Total Current Current (typ) (max) 4 0.1 0.002 0.002 0.015 0.005 13.5 3.4 1.1 1.7 0.1 0.05
Conditions ADCs On Only AUXDAC On Only REFCAP On Only REFCAP and REFOUT On Only All Sections Off All Sections Off
BSE 1 0 0 0 0 0
ASE 0 1 0 0 0 0
MCLK ON YES YES NO NO YES NO
Comments REFOUT Enabled, BSCLK = MCLK REFOUT Disabled, ASCLK = MCLK/48 REFOUT Disabled REFOUT Enabled MCLK Active Levels Equal to 0 V and DVDD Digital Inputs Static and Equal to 0 V or DVDD
The above values are in mA.
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AD7729
Table II. Receive Section Signal Ranges Table III. Auxiliary Section Signal Ranges
Baseband Section V REFCAP V REFOUT ADC ADC Signal Range V BIAS Differential Input Single-Ended Input Signal Range Differential Single-Ended
Signal Range 1.3 V ± 5% 1.3 V ± 10% 2 V REFCAP VREFCAP/2 to (AVDD1 VREFCAP/2) VREFCAP to (AVDD1 VREFCAP) VBIAS ± VREFCAP/2 V BIAS ± V REFCAP
AUXDAC Output Code Code 000 Code 3FF
Signal Range 2/32 × VREFCAP 2 V REFCAP
TIMING CHARACTERISTICS
Parameter AUXILIARY FUNCTIONS Clock Signals t1 t2 t3 t4 t5 t6 t10 t11 t12 t13 t14 t15 t16 t17 Receive Section Clock Signals t7 t8 t9 t18 t19 t20 t21 t22 t23 t24 t25
(AVDD1 = AVDD2 = +3 V 10%; DVDD1 = DVDD2 = +3 V TA = TMIN to TMAX , unless otherwise noted)
Units Description
10%; AGND = DGND = 0 V;
Limit at TA = 40 C to +105 C
76 30.4 30.4 t1 0.4 × t1 0.4 × t1 20 10 15 0 0 15 10 t4 + 15
ns min ns min ns min ns min ns min ns min ns min ns min ns max ns min ns min ns max ns min ns min
See Figure 2. MCLK Period MCLK Width Low MCLK Width High ASCLK Period. See Figures 4 and 6. ASCLK Width Low ASCLK Width High ASDI/ASDIFS Setup Before ASCLK Low ASDI/ASDIFS Hold After ASCLK Low ASDOFS Delay from ASCLK High ASDOFS Hold After ASCLK High ASDO Hold After ASCLK High ASDO Delay from ASCLK High ASDIFS Low to ASDI LSB Read by ASPORT Interval Between Consecutive ASDIFS Pulses See Figures 5 and 7. BSCLK Period BSCLK Width Low BSCLK Width High BSDI/BSDIFS Setup Before BSCLK Low BSDI/BSDIFS HoldAfter BSCLK Low BSDOFS Delay from BSCLK High BSDOFS Hold After BSCLK High BSDO Hold After BSCLK High BSDO Delay from BSCLK High BSDIFS Low to ASDI LSB Read by BSPORT Interval Between Consecutive BSDIFS Pulses
t1 0.4 × t1 0.4 × t1 20 10 15 0 0 15 10 t7 + 15
ns min ns min ns min ns min ns min ns max ns min ns min ns max ns min ns min
ASCLK = MCLK/(2 × ASCLKRATE). ASCLKRATE can have a value from 0 . . . 1023. When ASCLKRATE = 0, ASCLK = 13 MHz. BSCLK = MCLK/(2 × BSCLKRATE). BSCLKRATE can have a value from 0 . . . 1023. When BSCLKRATE = 0, BSCLK = 13 MHz. Specifications subject to change without notice.
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AD7729 TIMING DIAGRAMS
t1 t1 t3
*ASCLK MCLK
t3
t2
t5 t6 t4
t2
*ASCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE).
Figure 2. Clock Timing
100 A IOL MCLK TO OUTPUT PIN CL 15pF 100 A IOH *BSCLK +2.1V
Figure 4. ASCLK
t1 t3 t2
t8 t9 t7
Figure 3. Load Circuit for Timing Specifications
*BSCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE).
Figure 5. BSCLK
ASE (I) ASCLK (O) THREE-STATE
t 10 t 16
ASDIFS (I)
t 17
t 11 t 10
ASDI (I) THREE-STATE ASDOFS (O) THREE-STATE D9
t 11
D8 A1 A0 D9 D8 D7
t 12
t 13 t 14
D9 A2 A1 A0 D9 D8
ASDO (O)
NOTE I = INPUT, O = OUTPUT
t 15
Figure 6. Auxiliary Serial Port ASPORT
BSE (I) THREE-STATE
BSCLK (O)
t 18 t 24
BSDIFS (I)
t 25
t 19
BSDI (I) THREE-STATE BSDOFS (O) THREE-STATE BSDO (O) NOTE I = INPUT, O = OUTPUT D9
t 18
t 19
D8 A1 A0 D9 D8 D7
t 20
t 21 t 22
D9 A2 A1 A0 D9 D8
t 23
Figure 7. Baseband Serial Port BSPORT
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