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Details, datasheet, quote on part number:AD7730LBRU
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| Part: | AD7730LBRU |
| Category: | Data Conversion => ADC (Analog to Digital Converters) => >14 bit |
| Description: | CMOS, 24-Bit Low Power Sigma-delta ADC For Bridge Transducer Applications |
| Company: | Analog Devices |
| Datasheet: | Download AD7730LBRU datasheet File size : 509 kB |
| Request For quote: | Find where to buy AD7730LBRU
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Datasheet text preview:
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KEY FEATURES Resolution of 230,000 Counts (Peak-to-Peak) Offset Drift: 5 nV/ C Gain Drift: 2 ppm/ C Line Frequency Rejection: >150 dB Buffered Differential Inputs Programmable Filter Cutoffs Specified for Drift Over Time Operates with Reference Voltages of 1 V to 5 V ADDITIONAL FEATURES Two-Channel Programmable Gain Front End On-Chip DAC for Offset/TARE Removal FASTStepTM Mode AC or DC Excitation Single Supply Operation APPLICATIONS Weigh Scales Pressure Measurement GENERAL DESCRIPTION
Bridge Transducer ADC AD7730/AD7730L
The modulator output is processed by a low pass programmable digital filter, allowing adjustment of filter cutoff, output rate and settling time. The part features two buffered differential programmable gain analog inputs as well as a differential reference input. The part operates from a single +5 V supply. It accepts four unipolar analog input ranges: 0 mV to +10 mV, +20 mV, +40 mV and +80 mV and four bipolar ranges: ± 10 mV, ± 20 mV, ± 40 mV and ± 80 mV. The peak-to-peak resolution achievable directly from the part is 1 in 230,000 counts. An on-chip 6-bit DAC allows the removal of TARE voltages. Clock signals for synchronizing ac excitation of the bridge are also provided. The serial interface on the part can be configured for three-wire operation and is compatible with microcontrollers and digital signal processors. The AD7730 contains self-calibration and system calibration options, and features an offset drift of less than 5 nV/°C and a gain drift of less than 2 ppm/°C. The AD7730 is available in a 24-pin plastic DIP, a 24-lead SOIC and 24-lead TSSOP package. The AD7730L is available in a 24-lead SOIC and 24-lead TSSOP package.
NOTE
The AD7730 is a complete analog front end for weigh-scale and pressure measurement applications. The device accepts lowlevel signals directly from a transducer and outputs a serial digital word. The input signal is applied to a proprietary programmable gain front end based around an analog modulator.
The description of the functions and operation given in this data sheet apply to both the AD7730 and AD7730L. Specifications and performance parameters differ for the parts. Specifications for the AD7730L are outlined in Appendix A.
FUNCTIONAL BLOCK DIAGRAM
AVDD VBIAS AIN1(+) AIN1() MUX AIN2(+)/D1 AIN2()/D0 100nA AGND 6-BIT DAC SERIAL INTERFACE AND CONTROL LOGIC CLOCK GENERATION REGISTER BANK CALIBRATION MICROCONTROLLER ACX ACX AC EXCITATION CLOCK AGND DGND POL RDY RESET AVDD 100nA BUFFER + +/ PGA DVDD REF IN() REF IN(+) REFERENCE DETECT
AD7730
SIGMA-DELTA A/D CONVERTER STANDBY SYNC
SIGMADELTA MODULATOR
PROGRAMMABLE DIGITAL FILTER
MCLK IN MCLK OUT SCLK CS DIN DOUT
FASTStep is a trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998
AD7730SPECIFICATIONS 0 V; f
Parameter STATIC PERFORMANCE (CHP = 1) No Missing Codes2 Output Noise and Update Rates2 Integral Nonlinearity Offset Error2 Offset Drift vs. Temperature2 Offset Drift vs. Time4 Positive Full-Scale Error2, 5 Positive Full-Scale Drift vs Temp2, 6, 7 Positive Full-Scale Drift vs Time4 Gain Error2, 8 Gain Drift vs. Temperature2, 6, 9 Gain Drift vs. Time4 Bipolar Negative Full-Scale Error2 Negative Full-Scale Drift vs. Temp2, 6 Power Supply Rejection Common-Mode Rejection (CMR) Analog Input DC Bias Current2 Analog Input DC Bias Current Drift2 Analog Input DC Offset Current2 Analog Input DC Offset Current Drift2 STATIC PERFORMANCE (CHP = 0)2 No Missing Codes Output Noise and Update Rates Integral Nonlinearity Offset Error Offset Drift vs. Temperature6 Offset Drift vs. Time4 Positive Full-Scale Error5 Positive Full-Scale Drift vs. Temp6, 7 Positive Full-Scale Drift vs. Time4 Gain Error8 Gain Drift vs. Temperature6, 9 Gain Drift vs. Time4 Bipolar Negative Full-Scale Error Negative Full-Scale Drift vs. Temp Power Supply Rejection Common-Mode Rejection (CMR) on AIN CMR on REF IN Analog Input DC Bias Current Analog Input DC Bias Current Drift Analog Input DC Offset Current Analog Input DC Offset Current Drift ANALOG INPUTS/REFERENCE INPUTS Normal-Mode 50 Hz Rejection2 Normal-Mode 60 Hz Rejection2 Common-Mode 50 Hz Rejection2 Common-Mode 60 Hz Rejection2 Analog Inputs Differential Input Voltage Ranges11 B Version1 24 See Tables I & II 18 See Note 3 5 25 See Note 3 2 10 See Note 3 2 10 See Note 3 2 120 120 50 100 10 50
(AVDD = +5 V, DVDD = +3 V or +5 V; REF IN(+) = AVDD; REF IN() = AGND = DGND = CLK IN = 4.9152 MHz. All specifications TMIN to TMAX unless otherwise noted.)
Units Bits min ppm of FSR max nV/°C typ nV/1000 Hours typ ppm of FS/°C max ppm of FS/1000 Hours typ ppm/°C max ppm/1000 Hours typ ppm of FS/°C max dB typ dB min nA max pA/°C typ nA max pA/°C typ Bits min ppm of FSR max µV/°C typ µV/1000 Hours typ µV/°C typ µV/1000 Hours typ ppm/°C typ ppm/1000 Hours typ µV/°C typ dB typ dB typ dB typ nA max pA/°C typ nA max pA/°C typ dB min dB min dB min dB min Offset Error and Offset Drift Refer to Both Unipolar Offset and Bipolar Zero Errors Offset Error and Offset Drift Refer to Both Unipolar Offset and Bipolar Zero Errors Conditions/Comments
Measured with Zero Differential Voltage At DC. Measured with Zero Differential Voltage
24 See Tables III & IV 18 See Note 3 0.5 2.5 See Note 3 0.6 3 See Note 3 2 10 See Note 3 0.6 90 100 120 60 150 30 100 88 88 120 120
S K I P = 0 10
Measured with Zero Differential Voltage At DC. Measured with Zero Differential Voltage At DC. Measured with Zero Differential Voltage
From 49 Hz to 51 Hz From 59 Hz to 61 Hz From 49 Hz to 51 Hz From 59 Hz to 61 Hz Assuming 2.5 V or 5 V Reference with HIREF Bit Set Appropriately Gain = 250 Gain = 125 Gain = 62.5 Gain = 31.25
Absolute/Common-Mode Voltage12 Reference Input REF IN(+) REF IN() Voltage REF IN(+) REF IN() Voltage Absolute/Common-Mode Voltage13 NO REF Trigger Voltage
0 to +10 or ± 10 0 to +20 or ± 20 0 to +40 or ± 40 0 to +80 or ± 80 AGND + 1.2 V AVDD 0.95 V +2.5 +5 AGND 30 mV AVDD + 30 mV 0.3 0.65
mV nom mV nom mV nom mV nom V min V max V nom V nom V min V max V min V max
HIREF Bit of Mode Register = 0 HIREF Bit of Mode Register = 1
NO REF Bit Active If VREF Below This Voltage NO REF Bit Inactive If VREF Above This Voltage
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REV. A
AD7730/AD7730L
Parameter LOGIC INPUTS Input Current All Inputs Except SCLK and MCLK IN VINL, Input Low Voltage VINL, Input Low Voltage VINH, Input High Voltage SCLK Only (Schmitt Triggered Input) V T+ V T+ VT VT VT + VT VT + VT MCLK IN Only VINL, Input Low Voltage VINL, Input Low Voltage VINH, Input High Voltage VINH, Input High Voltage LOGIC OUTPUTS (Including MCLK OUT) VOL, Output Low Voltage 0.4 VOL, Output Low Voltage 0.4 VOH, Output High Voltage 4.0 VOH, Output High Voltage Floating State Leakage Current Floating State Output Capacitance2 TRANSDUCER BURNOUT AIN1(+) Current AIN1() Current Initial Tolerance @ 25°C Drift 2 OFFSET (TARE) DAC Resolution LSB Size DAC Drift16 DAC Drift vs. Time4, 16 Differential Linearity SYSTEM CALIBRATION Positive Full-Scale Calibration Limit17 Negative Full-Scale Calibration Limit17 Offset Calibration Limit18 Input Span17 POWER REQUIREMENTS Power Supply Voltages AVDD AGND Voltage DVDD Voltage Power Supply Currents AVDD Current (Normal Mode) AVDD Current (Normal Mode) DVDD Current (Normal Mode) DVDD Current (Normal Mode) AVDD + DVDD Current (Standby Mode) Power Dissipation Normal Mode Standby Mode VDD 0.6 V ± 10 6 100 100 ± 10 0.1 6 2.3/2.6 2.5 25 0.25/+0.75 1.05 × FS 1.05 × FS 1.05 × FS 0.8 × FS 2.1 × FS V min µA max pF typ nA nom nA nom % typ %/°C typ Bit mV min/mV max ppm/°C max ppm/1000 Hours typ LSB max V max V max V max V min V max V min V max V max B Version1 ± 10 0.8 0.4 2.0 1.4/3 1/2.5 0.8/1.4 0.4/1.1 0.4/0.8 0.4/0.8 0.8 0.4 3.5 2.5 Units µA max V max V max V min V min to V max V min to V max V min to V max V min to V max V min to V max V min to V max V max V max V min V min DVDD = +5 V DVDD = +3 V Conditions/Comments
DVDD = +5 V DVDD = +3 V DVDD = +5 V DVDD = +3 V DVDD = +5 V DVDD = +3 V DVDD = +5 V DVDD = +3 V DVDD = +5 V DVDD = +3 V ISINK = 800 µA Except for MCLK OUT14; VDD15 = +5 V ISINK = 100 µA Except for MCLK OUT14; VDD15 = +3 V ISOURCE = 200 µA Except for MCLK OUT14; VDD15 = +5 V ISOURCE = 100 µA Except for MCLK OUT14; VDD15 = +3 V
2.5 mV Nominal with 5 V Reference (REF IN/2000)
Guaranteed Monotonic FS Is the Nominal Full-Scale Voltage (10 mV, 20 mV, 40 mV or 80 mV)
+4.75 to +5.25 +2.7 to +5.25 10.3 22.3 1.3 2.7 25 65 125 125
V min to V max V min to V max mA max mA max mA max mA max µA max mW max mW max µW max
With AGND = 0 V External MCLK. Digital I/Ps = 0 V or DVDD All Input Ranges Except 0 mV to +10 mV and ± 10 mV Input Ranges of 0 mV to +10 mV and ± 10 mV Only DVDD of 2.7 V to 3.3 V DVDD of 4.75 V to 5.25 V Typically 10 µA. External MCLK IN = 0 V or DVDD AVDD = DVDD = +5 V. Digital I/Ps = 0 V or DVDD All Input Ranges Except 0 mV to +10 mV and ± 10 mV Input Ranges of 0 mV to +10 mV and ± 10 mV Only Typically 50 µW. External MCLK IN = 0 V or DVDD
REV. A
3
AD7730/AD7730L
NOTES 11 Temperature range: 40°C to +85°C. 12 Sample tested during initial release. 13 The offset (or zero) numbers with CHP = 1 are typically 3 µV precalibration. Internal zero-scale calibration reduces this by about 1 µV. Offset numbers with CHP = 0 can be up to 1 mV precalibration. Internal zero-scale calibration reduces this to 2 µV typical. System zero-scale calibration reduces offset numbers with CHP = 1 and CHP = 0 to the order of the noise. Gain errors can be up to 3000 ppm precalibration with CHP = 0 and CHP = 1. Performing internal full-scale calibrations on the 80 mV range reduces the gain error to less than 100 ppm for the 80 mV and 40 mV ranges, to about 250 ppm for the 20 mV range and to about 500 ppm on the 10 mV range. System full-scale calibration reduces this to the order of the noise. Positive and negative full-scale errors can be calculated from the offset and gain errors. 14 These numbers are generated during life testing of the part. 15 Positive Full-Scale Error includes Offset Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges. See Terminology. 16 Recalibration at any temperature will remove these errors. 17 Full-Scale Drift includes Offset Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges. 18 Gain Error is a measure of the difference between the measured and the ideal span between any two points in the transfer function. The two points used to calculate the gain error are positive full scale and negative full scale. See Terminology. 19 Gain Error Drift is a span drift and is effectively the drift of the part if zero-scale calibrations only were performed. 10 No Missing Codes performance with CHP = 0 and SKIP = 1 is reduced below 24 bits for SF words lower than 180 decimal. 11 The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1() and AIN2() inputs respectively. 12 The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed. 13 The common-mode voltage range on the reference input pair (REF IN(+) and REF IN()) applies provided the absolute input voltage specification is obeyed. 14 These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load. 15 VDD refers to DVDD for all logic outputs expect D0, D1, ACX and ACX where it refers to AVDD. In other words, the output logic high for these four outputs is determined by AV DD. 16 This number represents the total drift of the channel with a zero input and the DAC output near full scale. 17 After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, the device outputs all 0s. 18 These calibration and span limits apply provided the absolute input voltage specification is obeyed. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point. Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2 Input Logic 0 = 0 V, Logic 1 = DV
Parameter Master Clock Range t1 t2 Read Operation t3 t4 t5 4 t 5A 4, 5 t6 t7 t8 t9 6 t10 Write Operation t11 t12 t13 t14 t15 t16 Limit at TMIN to TMAX (B Version) 1 5 50 50 0 0 0 60 80 0 60 80 100 100 0 10 80 100 0 30 25 100 100 0 Units MHz min MHz max ns min ns min ns min ns min ns min ns max ns max ns min ns max ns max ns min ns min ns min ns min ns max ns max ns min ns min ns min ns min ns min ns min
(AVDD = +4.75 V to +5.25 V; DVDD = +2.7 V to +5.25 V; AGND = DGND = 0 V; fCLK IN = 4.9152 MHz; DD unless otherwise noted).
Conditions/Comments For Specified Performance SYNC Pulsewidth RESET Pulsewidth RDY to CS Setup Time CS Falling Edge to SCLK Active Edge Setup Time3 SCLK Active Edge to Data Valid Delay3 DVDD = +4.75 V to +5.25 V DVDD = +2.75 V to +3.3 V CS Falling Edge to Data Valid Delay DVDD = +4.75 V to +5.25 V DVDD = +2.7 V to +3.3 V SCLK High Pulsewidth SCLK Low Pulsewidth CS Rising Edge to SCLK Inactive Edge Hold Time3 Bus Relinquish Time after SCLK Inactive Edge3 SCLK Active Edge to RDY High3, 7 CS Falling Edge to SCLK Active Edge Setup Time3 Data Valid to SCLK Edge Setup Time Data Valid to SCLK Edge Hold Time SCLK High Pulsewidth SCLK Low Pulsewidth CS Rising Edge to SCLK Edge Hold Time
NOTES 1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV DD) and timed from a voltage level of 1.6 V. 2 See Figures 18 and 19. 3 SCLK active edge is falling edge of SCLK with POL = 1; SCLK active edge is rising edge of SCLK with POL = 0. 4 These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits. 5 This specification only comes into play if CS goes low while SCLK is low (POL = 1) or if CS goes low while SCLK is high (POL = 0). It is primarily required for interfacing to DSP machines. 6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7 RDY returns high after the first read from the device after an output update. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur close to the next output update.
4
REV. A
AD7730/AD7730L
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . 5 V to +0.3 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . 2 V to +5 V Analog Input Voltage to AGND . . . . 0.3 V to AVDD + 0.3 V Reference Input Voltage to AGND . . 0.3 V to AVDD + 0.3 V AIN/REF IN Current (Indefinite) . . . . . . . . . . . . . . . . 30 mA Digital Input Voltage to DGND . . . . 0.3 V to DVDD + 0.3 V Digital Output Voltage to DGND . . . 0.3 V to DVDD + 0.3 V Output Voltage (ACX, ACX, D0, D1) to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to AVDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . 40°C to +85°C Storage Temperature Range . . . . . . . . . . . 65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . 105°C/W Lead Temperature (Soldering, 10 sec) . . . . . . . +260°C TSSOP Package, Power Dissipation . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . 128°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . +220°C SOIC Package, Power Dissipation . . . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . 75°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . +220°C
* Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD7730BN AD7730BR AD7730BRU EVAL-AD7730EB AD7730LBR AD7730LBRU EVAL-AD7730LEB
Temperature Range 40°C to +85°C 40°C to +85°C 40°C to +85°C Evaluation Board 40°C to +85°C 40°C to +85°C Evaluation Board
Package Description Plastic DIP Small Outline Thin Shrink Small Outline Small Outline Thin Shrink Small Outline
Package Options N-24 R-24 RU-24 R-24 RU-24
ISINK (800 A AT DVDD = +5V 100 A AT DVDD = +3V)
TO OUTPUT PIN 50pF
+1.6V
ISOURCE (200 A AT DVDD = +5V 100 A AT DVDD = +3V)
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7730 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
5
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