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Details, datasheet, quote on part number:AD7731B
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Datasheet text preview:
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FEATURES 24-Bit Sigma-Delta ADC 16 Bits p-p Resolution at 800 Hz Output Rate Programmable Output Rates up to 6.4 kHz Programmable Gain Front End 0.0015% Nonlinearity Buffered Differential Inputs Programmable Filter Cutoffs FASTStepTM* Mode for Channel Sequencing Single Supply Operation APPLICATIONS Process Control PLCs/DCS Industrial Instrumentation
Low Noise, High Throughput 24-Bit Sigma-Delta ADC AD7731
GENERAL DESCRIPTION
The AD7731 is a complete analog front-end for process control applications. The device has a proprietary programmable gain front end that allows it to accept a range of input signal ranges, including low level signals, directly from a transducer. The sigmadelta architecture of the part consists of an analog modulator and a low pass programmable digital filter, allowing adjustment of filter cutoff, output rate and settling time. The part features three buffered differential programmable gain analog inputs (which can be configured as five pseudo-differential inputs), as well as a differential reference input. The part operates from a single +5 V supply and accepts seven unipolar analog input ranges: 0 to +20 mV, +40 mV, +80 mV, +160 mV, +320 mV, +640 mV and +1.28 V, and seven bipolar ranges: ± 20 mV, ± 40 mV, ± 80 mV, ± 160 mV, ± 320 mV, ± 640 mV and ± 1.28 V. The peak-to-peak resolution achievable directly from the part is 16 bits at an 800 Hz output rate. The part can switch between channels with 1 ms settling time and maintain a performance level of 13 bits of peak-to-peak resolution. The serial interface on the part can be configured for three-wire operation and is compatible with microcontrollers and digital signal processors. The AD7731 contains self-calibration and system calibration options and features an offset drift of less than 5 nV/°C and a gain drift of less than 2 ppm/°C. The part is available in a 24-lead plastic DIP, a 24-lead SOIC and 24-lead TSSOP package.
FUNCTIONAL BLOCK DIAGRAM
AVDD NC AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 100nA AGND SERIAL INTERFACE AND CONTROL LOGIC CLOCK GENERATION REGISTER BANK CALIBRATION MICROCONTROLLER MCLK IN MCLK OUT MUX AVDD 100nA BUFFER PGA DVDD REF IN() REF IN(+)
AD7731
SIGMA-DELTA A/D CONVERTER SIGMADELTA MODULATOR PROGRAMMABLE DIGITAL FILTER STANDBY SYNC
SCLK CS DIN DOUT
AGND
DGND
POL
RDY
RESET
*FASTStep is a trademark of Analog Devices, Inc.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997
AD7731SPECIFICATIONS DGND = 0 V; f
Parameter STATIC PERFORMANCE (CHP = 0) No Missing Codes2 Output Noise and Update Rates2 Integral Nonlinearity Offset Error2 Offset Drift vs. Temperature2 Offset Drift vs. Time5 Positive Full-Scale Error2, 6 Positive Full-Scale Drift vs. Temp2, 7, 8 Positive Full-Scale Drift vs. Time5 Gain Error2, 9 Gain Drift vs. Temperature2, 7, 10 Gain Drift vs. Time5 Bipolar Negative Full-Scale Error2 Negative Full-Scale Drift vs. Temp2, 7 Power Supply Rejection11 Power Supply Rejection11 Common-Mode Rejection (CMR)11 On AIN On AIN On REF IN Analog Input DC Bias Current2 Analog Input DC Bias Current Drift2 Analog Input DC Offset Current2 Analog Input DC Offset Current Drift2 STATIC PERFORMANCE (CHP = 1)2 No Missing Codes Output Noise and Update Rates Integral Nonlinearity Offset Error Offset Drift vs. Temperature Offset Drift vs. Time5 Positive Full-Scale Error6 Positive Full-Scale Drift vs. Temp7, 8 Positive Full-Scale Drift vs. Time5 Gain Error9 Gain Drift vs. Temperature7, 10 Gain Drift vs. Time5 Bipolar Negative Full-Scale Error Negative Full-Scale Drift vs. Temp Power Supply Rejection11 Power Supply Rejection11 Common-Mode Rejection (CMR)11 On AIN On AIN On REF IN Analog Input DC Bias Current Analog Input DC Bias Current Drift Analog Input DC Offset Current Analog Input DC Offset Current Drift ANALOG INPUTS/REFERENCE INPUTS Normal Mode 50 Hz/60 Hz Rejection2 Common-Mode 50 Hz/60 Hz Rejection2 Analog Inputs Differential Input Voltage Ranges12 B Version1 24 See Tables I and II 15 See Note 4 0.5 1/2/5 2.5 See Note 4 0.6 1.5/3/6 3 See Note 4 2 10 See Note 4 1 90 60 95 85 120 60 150 30 100 24 See Tables III and IV 15 See Note 4 5 25 See Note 4 2 10 See Note 4 2 10 See Note 4 2 110 85 110 85 120 50 100 10 50 88 120
(AVDD = +5 V, DVDD = +3 V or +5 V; REF IN(+) = +2.5 V; REF IN() = AGND; AGND = CLK IN = 4.9152 MHz. All specifications TMIN to TMAX unless otherwise noted.)
Units Bits min ppm of FSR max µV/°C typ µV/°C typ µV/1000 Hr µV/°C typ µV/°C typ µV/1000 Hr ppm/°C typ ppm/1000 Hr µV/°C typ dB typ dB typ dB typ dB typ dB typ nA max pA/°C typ nA max pA/°C typ Bits min ppm of FSR max nV/°C typ nV/1000 Hr typ ppm of FS/°C max ppm of FS/1000 Hr ppm/°C max ppm/1000 Hr ppm of FS/°C max dB typ dB typ dB typ dB typ dB typ nA max pA/°C typ nA max pA/°C typ dB min dB min Offset Error and Offset Drift Refer to Both Unipolar Offset and Bipolar Zero Errors Offset Error and Offset Drift Refer to Both Input Range = 20 mV, 40 mV, 80 mV, 160 mV Input Range = 320 mV/640 mV/1.28 V Conditions/Comments SKIP = 0 3
Input Range = 20 mV, 40 mV, 80 mV, 160 mV Input Range = 320 mV/640 mV/1.28 V
Input Range = 20 mV Input Range = 1.28 V At DC. Input Range = 20 mV At DC. Input Range = 1.28 V
Input Range = 20 mV Input Range = 1.28 V At DC. Input Range = 20 mV At DC. Input Range = 1.28 V
50 Hz/60 Hz ± 1 Hz. SKIP = 0 50 Hz/60 Hz ± 1 Hz. SKIP = 0 Assuming 2.5 V or 5 V Reference with HIREF Bit Set Appropriately RN2, RN1, RN0 of Mode Register = 0, 0, 1 RN2, RN1, RN0 of Mode Register = 0, 1, 0 RN2, RN1, RN0 of Mode Register = 0, 1, 1 RN2, RN1, RN0 of Mode Register = 1, 0, 0 RN2, RN1, RN0 of Mode Register = 1, 0, 1 RN2, RN1, RN0 of Mode Register = 1, 1, 0 RN2, RN1, RN0 of Mode Register = 1, 1, 1
0 to +20 or ± 20 0 to +40 or ± 40 0 to +80 or ± 80 0 to +160 or ± 160 0 to +320 or ± 320 0 to +640 or ± 640 0 to +1.28 or ± 1.28
mV nom mV nom mV nom mV nom mV nom mV nom V nom
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Parameter Absolute/Common-Mode Voltage13 Reference Input REF IN(+) REF IN () Voltage REF IN(+) REF IN () Voltage Reference DC Input Current Reference DC Input Current Absolute/Common-Mode Voltage14 NO REF Trigger Voltage LOGIC INPUTS Input Current All Inputs Except SCLK and MCLK IN VINL, Input Low Voltage VINL, Input Low Voltage VINH, Input High Voltage SCLK Only (Schmitt Triggered Input) V T+ V T+ VT VT VT + VT VT + VT MCLK IN Only VINL, Input Low Voltage VINL, Input Low Voltage VINH, Input High Voltage VINH, Input High Voltage B Version1 AGND + 1.2 V AVDD 0.95 V +2.5 +5 5.5 10 AGND 30 mV AVDD + 30 mV 0.3 0.65 ± 10 0.8 0.4 2.0 1.4/3 0.95/2.5 0.8/1.4 0.4/1.1 0.4/0.85 0.4/0.8 0.8 0.4 3.5 2.5 Units V min V max V nom V nom µA max µA max V min V max V min V max µA max V max V max V min V min/V max V min/V max V min/V max V min/V max V min/V max V min/V max V max V max V min V min V max V max V min V min µA max pF typ nA nom nA nom % typ %/°C typ V max V max V min V min V max FS Is the Nominal Full-Scale Voltage (20 mV, 40 mV, 80 mV, 160 mV, 320 mV, 640 mV, 1.28 V) DVDD = +5 V DVDD = +3 V HIREF Bit of Mode Register = 0 HIREF Bit of Mode Register = 1 HIREF Bit of Mode Register = 0 HIREF Bit of Mode Register = 1 Conditions/Comments
NO REF Bit Active If VREF Below This Voltage NO REF Bit Inactive If VREF Above This Voltage
DVDD = +5 V DVDD = +3 V DVDD = +5 V DVDD = +3 V DVDD = +5 V DVDD = +3 V DVDD = +5 V DVDD = +3 V DVDD = +5 V DVDD = +3 V ISINK = 800 µA Except for MCLK OUT15. VDD16 = +5 V ISINK = 100 µA Except for MCLK OUT15. VDD16 = +3 V ISOURCE = 200 µA Except for MCLK OUT15. VDD16 = +5 V ISOURCE = 100 µA Except for MCLK OUT15. VDD16 = +3 V
LOGIC OUTPUTS (Including MCLK OUT) 0.4 VOL, Output Low Voltage VOL, Output Low Voltage VOH, Output High Voltage VOH, Output High Voltage Floating State Leakage Current Floating State Output Capacitance3 TRANSDUCER BURNOUT17 AIN1(+) Current AIN1() Current Initial Tolerance @ 25°C Drift SYSTEM CALIBRATION Positive Full-Scale Calibration Limit18 Negative Full-Scale Calibration Limit18 Offset Calibration Limit19 Input Span19 POWER REQUIREMENTS Power Supply Voltages AVDD AGND Voltage DVDD Voltage Power Supply Currents AVDD Current (Normal Mode) DVDD Current (Normal Mode) DVDD Current (Normal Mode) AVDD + DVDD Current (Standby Mode) Power Dissipation Normal Mode Standby Mode 0.4 4.0 DVDD 0.6 V ± 10 6 100 100 ± 10 0.1 1.05 × FS 1.05 × FS 1.05 × FS 0.8 × FS 2.1 × FS
+5 +2.7 to +5.25 10.3 1.7 3.2 25 67.5 125
V nom V min to V max mA max mA max mA max µA max mW max µW max
With AGND = 0 V External MCLK. Digital I/Ps = 0 V or DVDD DVDD of 2.7 V to 3.3 V DVDD of 4.75 V to 5.25 V Typically 10 µA. External MCLK IN = 0 V or DVDD AVDD = DVDD = +5 V. Digital I/Ps = 0 V or DVDD Typically 50 µW. External MCLK IN = 0 V or DVDD
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NOTES 1 Temperature Range: 40°C to +85°C. 2 Sample tested during initial release. 3 No missing codes performance with CHP = 0 and SKIP = 1 is 22 bits. 4 The offset (or zero) numbers with CHP = 0 can be up to 1 mV precalibration. Internal zero-scale calibration reduces this to 2 µV typical. Offset numbers with CHP = 1 are typically 3 µV precalibration. Internal zero-scale calibration reduces this by about 1 µV. System zero-scale calibration reduces offset numbers with CHP = 0 and CHP = 1 to the order of the noise. Gain errors can be up to 3000 ppm precalibration with CHP = 0 and CHP = 1. Performing internal full-scale calibrations on all input ranges except the 20 mV and 40 mV input range reduces the gain error to less than 100 ppm. When operating on the 20 mV or 40 mV range, an internal full-scale calibration should be performed on the 80 mV input range with a resulting gain error of less than 250 ppm. System full-scale calibration reduces the gain error on all input ranges to the order of the noise. Positive and Negative Full-Scale Errors can be calculated from the offset and gain errors. 5 These numbers are generated during life testing of the part. 6 Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges. See Terminology. 7 Recalibration at any temperature will remove these errors. 8 Full-scale drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges. 9 Gain Error is a measure of the difference between the measured and the ideal span between any two points in the transfer function. The two points use to calculate the gain error are positive full-scale and negative full-scale. See Terminology. 10 Gain Error Drift is a span drift and is effectively the drift of the part if zero-scale calibrations only were performed. 11 Power Supply Rejection and Common-Mode Rejection are given here for the upper and lower input voltage ranges. The rejection can be approximated to varying linearly (in dBs) between these values for the other input ranges. 12 The analog input voltage range on the AIN(+) inputs is given here with respect to the voltage on the respective AIN() input. 13 The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed. 14 The common-mode voltage range on the reference input pair (REF IN(+) and REF IN()) applies provided the absolute input voltage specification is obeyed. 15 These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load. 16 VDD refers to DVDD for all logic outputs expect D0 and D1 where it refers to AVDD. In other words, the output logic high for these two outputs is determined by AVDD. 17 See Burnout Current section. 18 After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, then the device outputs all 0s. 19 These calibration and span limits apply provided the absolute input voltage specification is obeyed. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point. Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2
Parameter Master Clock Range t1 t2 Read Operation t3 t4 t5 4 t 5A 4, 5 t6 t7 t8 t9 6 t10 Write Operation t11 t12 t13 t14 t15 t16 1 5 50 50 0 0 0 60 80 0 60 80 100 100 0 10 80 100 0 30 25 100 100 0
(AVDD = +4.75 V to +5.25 V; DVDD = +2.7 V to +5.25 V; AGND = DGND = 0 V; fCLK IN = 4.9152 MHz; Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted)
Units MHz min MHz max ns min ns min ns min ns min ns min ns max ns max ns min ns max ns max ns min ns min ns min ns min ns max ns max ns min ns min ns min ns min ns min ns min Conditions/Comments For Specified Performance SYNC Pulse Width RESET Pulse Width RDY to CS Setup Time CS Falling Edge to SCLK Active Edge Setup Time3 SCLK Active Edge to Data Valid Delay3 DVDD = +4.75 V to +5.25 V DVDD = +2.7 V to +3.3 V CS Falling Edge to Data Valid Delay3 DVDD = +4.75 V to +5.25 V DVDD = +2.7 V to +3.3 V SCLK High Pulse Width SCLK Low Pulse Width CS Rising Edge to SCLK Inactive Edge Hold Time3 Bus Relinquish Time after SCLK Inactive Edge3 SCLK Active Edge to RDY High3, 7 CS Falling Edge to SCLK Active Edge Setup Time3 Data Valid to SCLK Edge Setup Time Data Valid to SCLK Edge Hold Time SCLK High Pulse Width SCLK Low Pulse Width CS Rising Edge to SCLK Edge Hold Time
Limit at TMIN, TMAX (B Version)
NOTES 1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV DD) and timed from a voltage level of 1.6 V. 2 See Figures 15 and 16. 3 SCLK active edge is falling edge of SCLK with POL = 1; SCLK active edge is rising edge of SCLK with POL = 0. 4 These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V OL or VOH limits. 5 This specification only comes into play if CS goes low while SCLK is low (POL = 1) or if CS goes low while SCLK is high (POL = 0). It is required primarily for interfacing to DSP machines. 6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7 RDY returns high after the first read from the device after an output update. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur close to the next output update.
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ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . 5 V to +0.3 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . 2 V to +5 V Analog Input Voltage to AGND . . . . 0.3 V to AVDD + 0.3 V Reference Input Voltage to AGND . . 0.3 V to AVDD + 0.3 V AIN/REF IN Current (Indefinite) . . . . . . . . . . . . . . . . . 30 mA Digital Input Voltage to DGND . . . . 0.3 V to DVDD + 0.3 V Digital Output Voltage to DGND . . . 0.3 V to DVDD + 0.3 V Output Voltage (D0, D1) to DGND . . 0.3 V to AVDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . 40°C to +85°C Storage Temperature Range . . . . . . . . . . . 65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +260°C TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 128°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD7731BN AD7731BR AD7731BRU EVAL-AD7731EB
Temperature Range 40°C to +85°C 40°C to +85°C 40°C to +85°C Evaluation Board
Package Description Plastic DIP Small Outline Thin Shrink Small Outline (TSSOP)
Package Options N-24 R-24 RU-24
ISINK (800µA AT DVDD = +5V 100µA AT DVDD = +3V)
TO OUTPUT PIN 50pF
+1.6V
ISOURCE (200µA AT DVDD = +5V 100µA AT DVDD = +3V)
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7731 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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