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Details, datasheet, quote on part number:AD7734BRU
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Datasheet text preview:
4-Channel, ±10 V Input Range, High Throughput, 24-Bit - ADC AD7734
FEATURES
High resolution ADC 24 bits no missing codes ±0.0025% nonlinearity Optimized for fast channel switching 18-bit p-p resolution (21 bits effective) at 500 Hz 16-bit p-p resolution (19 bits effective) at 2 kHz 14-bit p-p resolution (18 bits effective) at 15 kHz On-chip per channel system calibration 4 single-ended analog inputs Input ranges +5 V, ±5 V, +10 V, ±10 V Overvoltage tolerant Up to ±16.5 V not affecting adjacent channel Up to ±50 V absolute maximum 3-wire serial interface SPITM, QSPITM, MICROWIRETM, and DSP compatible Schmitt trigger on logic inputs Single-supply operation 5 V analog supply 3 V or 5 V digital supply Package: 28-lead TSSOP
FUNCTIONAL BLOCK DIAGRAM
REFIN() AIN0 REFIN(+) REFERENCE DETECT
AIN1 MUX AIN2
BUFFER 24-BIT - ADC
AIN3
AD7734
BIASHI BIASLO CALIBRATION CIRCUITRY SERIAL INTERFACE SCLK DOUT
DIN
CS
P0 SYNC/P1
I/O PORT
CLOCK GENERATOR
CONTROL LOGIC
RDY RESET
AGND AVDD MCLKOUT MCLKIN
DGND DVDD
Figure 1.
APPLICATIONS
PLCs/DCS Multiplexing applications Process control Industrial instrumentation
GENERAL DESCRIPTION
The AD7734 is a high precision, high throughput analog front end. True 16-bit p-p resolution is achievable with a total conversion time of 500 µs (2 kHz channel switching), making it ideally suitable for high resolution multiplexing applications. The part can be configured via a simple digital interface, which allows users to balance the noise performance against data throughput up to a 15.4 kHz. The analog front end features four single-ended input channels with unipolar or true bipolar input ranges to ±10 V while operating from a single +5 V analog supply. The part has an overrange and underrange detection capability and accepts an analog input overvoltage to ±16.5 V without degrading the performance of the adjacent channels.
The differential reference input features "No-Reference" detect capability. The ADC also supports per channel system calibration options. The digital serial interface can be configured for 3-wire operation and is compatible with microcontrollers and digital signal processors. All interface inputs are Schmitt triggered. The part is specified for operation over the extended industrial temperature range of 40°C to +105°C. Other parts in the AD7734 family are the AD7732 and the AD7738. The AD7732 is similar to AD7734, but its analog front end features two fully differential input channels. The AD7738 analog front end is configurable for four fully differential or eight single-ended input channels, features 0.625 V to 2.5 V bipolar/unipolar input ranges, and accepts a common-mode input voltage from 200 mV to AVDD300 mV. The AD7738 multiplexer output is pinned out externally, allowing the user to implement programmable gain or signal conditioning before being applied to the ADC.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
AD7734
TABLE OF CONTENTS
AD7734--Specifications......... 3 Timing Specifications..... 6 Absolute Maximum Ratings... 8 Typical Performance Characteristics ............ 9 Output Noise and Resolution Specification........ 10 Chopping Enabled.... 10 Chopping Disabled............ 11 Pin Configurations and Functional Descriptions .... 12 Register Description..... 14 Register Access.......... 15 Communications Register......... 15 I/O Port Register....... 16 Revision Register ...... 16 Test Register ........ 16 ADC Status Register.......... 17 Checksum Register............ 17 ADC Zero-Scale Calibration Register .... 17 ADC Full-Scale Register... 17 Channel Data Registers .... 17 Channel Zero-Scale Calibration Registers ...... 18 Channel Full-Scale Calibration Registers........ 18 Channel Status Registers .. 18 Channel Setup Registers ... 19 Channel Conversion Time Registers ...... 19 Mode Register ........... 20 Digital Interface Description ........ 22 Hardware .... 22 Reset ............ 23 Access the AD7734 Registers.... 23 Single Conversion and Reading Data ..... 23 Dump Mode........ 24 Continuous Conversion Mode ....... 24 Continuous Read (Continuous Conversion) Mode ..... 25 Circuit Description....... 26 Analog Front End..... 26 Analog Input's Extended Voltage Range ......... 27 Chopping .... 27 Multiplexer, Conversion, and Data Output Timing...... 28 Sigma-Delta ADC..... 28 Frequency Response ......... 29 Voltage Reference Inputs.. 29 Reference Detect....... 29 I/O Port....... 30 Calibration.. 30 ADC Zero-Scale Self-Calibration ........... 30 Per Channel System Calibration .... 30 Outline Dimensions ..... 32
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD7734
AD7734--SPECIFICATIONS
Table 1. (40°C to +105°C; AVDD = 5 V ± 5%; DVDD = 2.7 V to 3.6 V, or 5 V ± 5%; BIAS0 to BIAS3, BIASHI, REFIN(+) = 2.5 V; BIASLO, REFIN() = AGND; AIN Range = ±10 V; fMCLKIN = 6.144 MHz; unless otherwise noted.)
Parameter ADC PERFORMANCE CHOPPING ENABLED Conversion Time Rate No Missing Codes1, 2 Output Noise Min Typ Max Unit Test Conditions/Comments
372 24
12190
Hz Bits
Configure via Conv. Time Register FW 6 (Conversion Time 165 µs)
See
Table 4 See Table 5 and Table 6 ±0.0010 ±0.0025
Resolution Integral Nonlinearity (INL) 1, 2 Integral Nonlinearity (INL)2 Offset Error (Unipolar, Bipolar)3 Offset Drift vs. Temperature1 Gain Error3 Gain Drift vs. Temperature1 Positive Full-Scale Error3 Positive Full-Scale Drift vs. Temp.1 Bipolar Negative Full-Scale Error4 Power Supply Sensitivity Channel-to-Channel Isolation ADC PERFORMANCE CHOPPING DISABLED Conversion Time Rate No Missing Codes1, 2 Output Noise
±0.0030 ±0.0045 ±10 ±2.5 ±0.35 ±3.2 ±0.5 ±3 ±10
±0.0050 ±4 100
% of FSR % of FSR mV µV/°C % ppm of FS/°C % of FSR ppm of FS/°C % of FSR LSB16 dB
fMCLKIN = 2.5 MHz fMCLKIN = 6.144 MHz Before Calibration Before Calibration Before Calibration After Calibration At DC, AIN = 7 V, AVDD = 5 V ± 5% At DC, Maximum ±16.5 V AIN Voltage
737 24
15437
Hz Bits
Configure via Conv. Time Register FW 8 (Conversion Time 117 µs)
See
Table 7 See Table 8 and Table 9 ±0.0025 ±15 ±25 ±0.1 ±5.3 ±0.2 ±4 ±0.0050 ±4 100
Resolution Integral Nonlinearity (INL)2 Offset Error (Unipolar, Bipolar)5 Offset Drift vs. Temperature Gain Error3 Gain Drift vs. Temperature Positive Full-Scale Error3 Positive Full-Scale Drift vs. Temp. Bipolar Negative Full-Scale Error4 Power Supply Sensitivity Channel-to-Channel Isolation ANALOG INPUTS Analog Input Voltage1, 6, 7 ±10 V Range 0 V to +10 V Range ±5 V Range 0 V to +5 V Range BIASLO Voltage BIAS0 to 3, BIASHI Voltage AIN Impedance1, 8 AIN Pin, BIASLO Pin Impedance1, 8
% of FSR mV µV/°C % ppm of FS/°C % of FSR ppm of FS/°C % of FSR LSB16 dB
Before Calibration Before Calibration Before Calibration After Calibration At DC, AIN = 7 V, AVDD = 5 V ± 5% At DC, Maximum ±16.5 V AIN Voltage
100 87.5
±10 0 to +10 ±5 0 to +5 0 2.5 124 108.5
Rev. 0 | Page 3 of 32
V V V V V V k k
AD7734
Parameter BIAS0 to 3, BIASHI Pin Impedance1, 8 Input Resistor Matching Input Resistor Temp. Coefficient REFERENCE INPUTS REFIN(+) to REFIN() Voltage1, 9 NOREF Trigger Voltage REFIN(+), REFIN() Common-Mode Voltage1 Reference Input DC Current10 SYSTEM CALIBRATION1, 11 Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span LOGIC INPUTS Input Current Input Current CS Input Capacitance VT+1 VT1 VT+ VT1 VT+1 VT 1 VT+ VT1 MCLK IN ONLY Input Current Input Capacitance VINL Input Low Voltage VINH Input High Voltage VINL Input Low Voltage VINH Input High Voltage LOGIC OUTPUTS12 VOL Output Low Voltage VOH Output High Voltage VOL Output Low Voltage VOH Output High Voltage Floating State Leakage Current Floating State Leakage Capacitance P0, P1 INPUTS/OUTPUTS Input Current VINL Input Low Voltage VINH Input High Voltage VOL Output Low Voltage VOH Output High Voltage POWER REQUIREMENTS AVDDAGND Voltage DVDDDGND Voltage AVDD Current (Normal Mode) DVDD Current (Normal Mode) 13 DVDD Current (Normal Mode) 13 5 1.4 0.8 0.3 0.95 0.4 0.3 2 1.4 0.85 2 1.1 0.85 ±10 5 0.8 3.5 0.4 2.5 0.4 4.0 0.4 DVDD 0.6 ±1 3 ±10 0.8 3.5 0.4 4.0 4.75 4.75 2.70 13.5 2.8 1.0 5.25 5.25 3.60 15.9 3.1 1.5
Rev. 0 | Page 4 of 32
Min 12.5
Typ 15.5 0.2 30
Max
Unit k % ppm/°C
Test Conditions/Comments
2.475
2.5 0.5
2.525
V V V µA V V V µA µA µA pF V V V V V V µA pF V V V V V V V V µA pF µA V V V V V V V mA mA mA
NOREF Bit in Channel Status Register
0
AVDD 400 +1.05 × FS
1.05 × FS 0.8 × FS
2.1 × FS ±1 ±10 40
CS = DVDD CS = DGND, Internal Pull-Up Resistor DVDD = 5 V DVDD = 5 V DVDD = 5 V DVDD = 3 V DVDD = 3 V DVDD = 3 V
DVDD = 5 V DVDD = 5 V DVDD = 3 V DVDD = 3 V ISINK = 800 µA, DVDD = 5 V ISOURCE = 200 µA, DVDD = 5 V ISINK = 100 µA, DVDD = 3 V ISOURCE = 100 µA, DVDD = 3 V
Levels Referenced to Analog Supplies AVDD = 5 V AVDD = 5 V ISINK = 7 mA, See Abs. Max. Ratings ISOURCE = 200 µA, AVDD = 5 V
AVDD = 5 V DVDD = 5 V DVDD = 3 V
AD7734
Parameter Power Dissipation (Normal Mode) 13 AVDD+DVDD Current (Standby Mode)14 Power Dissipation (Standby Mode) 14 Min Typ 85 100 525 Max 100 Unit mW µA µW Test Conditions/Comments
1 2 3
Specifications are not production tested but guaranteed by design and/or characterization data at initial product release. See Typical Performance Characteristics. Specifications before calibration. Channel system calibration reduces these errors to the order of the noise. 4 Applies after the zero-scale and full-scale calibration. The negative full-scale error represents the remaining error after removing the offset and gain error. 5 ADC zero-scale self-calibration reduces this error to ±10 mV. Channel zero-scale system calibration reduces this error to the order of the noise. 6 For specified performance. The output data span corresponds to the specified nominal input voltage range. The ADC is functional outside the nominal input voltage range, but the performance might degrade. Outside the nominal input voltage range, the OVR bit in the channel status register is set and the channel data register value depends on the CLAMP bit in the mode register. See the register and circuit descriptions for more details. 7 The adjacent channels are not affected by AIN voltage up to ±16.5 V. 8 Pin impedance is from the pin to the internal node. In normal circuit configuration, the analog input total impedance is typically 108.5 k + 15.5 k = 124 k. 9 For specified performance. Part is functional with lower VREF. 10 Dynamic current charging the sigma-delta modulator input switching capacitor. 11 Outside the specified calibration range, calibration is possible but the performance may degrade. 12 These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load. 13 With external MCLK, MCLKOUT disabled (CLKDIS bit set in the mode register). 14 External MCLKIN = 0 V or DVDD, digital inputs = 0 V or DVDD, P0 and P1 = 0 V or AVDD.
Rev. 0 | Page 5 of 32
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