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Details, datasheet, quote on part number:AD7738
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Datasheet text preview:
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FEATURES High Resolution ADC 24 Bits No Missing Codes 0.0015% Nonlinearity Optimized for Fast Channel Switching 18-Bits p-p Resolution (21 Bits Effective) at 500 Hz 16-Bits p-p Resolution (19 Bits Effective) at 8.5 kHz 15-Bits p-p Resolution (18 Bits Effective) at 15 kHz On-Chip Per Channel System Calibration Configurable Inputs 8 Single-Ended or 4 Fully Differential Input Ranges +625 mV, +1.25 V, +2.5 V, 625 mV, 1.25 V, 2.5 V 3-Wire Serial Interface SPITM, QSPITM, MICROWIRETM and DSP Compatible Schmitt Trigger on Logic Inputs Single-Supply Operation 5 V Analog Supply 3 V or 5 V Digital Supply Package: 28-Lead TSSOP APPLICATIONS PLCs/DCS Multiplexing Applications Process Control Industrial Instrumentation
8-Channel, High Throughput, 24-Bit - ADC AD7738
FUNCTIONAL BLOCK DIAGRAM
MUXOUT ADCIN REFIN REFIN+ REFERENCE DETECT
AIN0 AIN1 AIN2 AIN3 MUX AIN4 AIN5 AIN6 AIN7 CALIBRATION CIRCUITRY BUFFER
24-BIT - ADC
AD7738
SCLK SERIAL INTERFACE DOUT DIN CS
AINCOM/P0
I/O PORT SYNC/P1
CLOCK GENERATOR
CONTROL LOGIC
RDY RESET
AGND
AVDD
MCLKOUT
MCLKIN
DGND
DVDD
GENERAL DESCRIPTION
The AD7738 is a high precision, high throughput analog front end. True 16-bit p-p resolution is achievable with a total conversion time of 117 µs (8.5 kHz channel switching), making it ideally suitable for high resolution multiplexing applications. The part can be configured via a simple digital interface, which allows users to balance the noise performance against data throughput up to a 15.4 kHz. The analog front end features eight single-ended or four fully differential input channels with unipolar or bipolar 625 mV, 1.25 V, and 2.5 V input ranges and accepts a common-mode input voltage from 200 mV above AGND to AVDD 300 mV. The multiplexer output is pinned out externally, allowing the user to implement programmable gain or signal conditioning before applying the input to the ADC.
The differential reference input features "No-Reference" detect capability. The ADC also supports per channel system calibration options. The digital serial interface can be configured for 3-wire operation and is compatible with microcontrollers and digital signal processors. All interface inputs are Schmitt triggered. The part is specified for operation over the extended industrial temperature range of 40 C to +105 C. Other parts in the AD7738 family are the AD7734 and the AD7732. The AD7734 analog front end features four single-ended input channels with unipolar or true bipolar input ranges to ± 10 V while operating from a single 5 V analog supply. The AD7734 accepts an analog input overvoltage to ± 16.5 V while not degrading the performance of the adjacent channels. The AD7732 is similar to AD7734, but its analog front end features two fully differential input channels.
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002
AFDN7738V,SPE= 0IV,FAINCOMTIOV,NMUXOUT(+)C=toADCIN(+),, AV = 5 V =5%, DV =InternaltoBufferor 5 VAIN Range = C ICA= 2.5 S (40 +105 C MUXOUT() ADCIN(), 2.7 V 3.6 V ON, 5%, RE I (+) = 2.5 REFIN()
DD DD
fMCLK = 6.144 MHz; unless otherwise noted.)
Parameter Min Typ Max Unit Test Conditions/Comment
1.25 V,
ADC PERFORMANCE-- CHOPPING ENABLED
Conversion Time Rate No Missing Codes1 Output Noise Resolution Integral Nonlinearity (INL) Offset Error (Unipolar, Bipolar) 2 Offset Drift vs. Temperature 1 Gain Error2 Gain Drift vs. Temperature1 Positive Full-Scale Error 2 Positive Full-Scale Drift vs. Temperature 1 Bipolar Negative Full-Scale Error 3 Common-Mode Rejection 80 Power Supply Rejection 70 ADC PERFORMANCE-- CHOPPING DISABLED Conversion Time Rate No Missing Codes1 Output Noise Resolution Integral Nonlinearity (INL) Offset Error (Unipolar, Bipolar) 4 Offset Drift vs. Temperature Gain Error2 Gain Drift vs. Temperature Positive Full-Scale Error 2 Positive Full-Scale Drift vs. Temperature Bipolar Negative Full-Scale Error 3 Common-Mode Rejection Power Supply Rejection ANALOG INPUTS Analog Input Voltage Ranges 1, 5 ± 2.5 V Range +2.5 V Range ± 1.25 V Range +1.25 V Range ± 0.625 V Range +0.625 V Range AIN, AINCOM Common-Mode Voltage 1 AIN, AINCOM Input Current 6 AIN to MUXOUT On Resistance 1 REFERENCE INPUT REFIN(+) to REFIN() Voltage 1, 7 NOREF Trigger Voltage REFIN(+), REFIN() Common-Mode Voltage1 Reference Input Current8 SYSTEM CALIBRATION1, 9 Full Scale Calibration Limit Zero Scale Calibration Limit Input Span 372 24 12190 Hz Bits Configure via Conversion Time Register FW 6 (Conversion Time 165 µs) See Typical Performance Characteristics
See Table I See Tables II and III ± 0.0015 ± 0.0015 ± 10 ± 280 ± 0.2 ± 2.5 ± 0.2 ± 2.5 ± 0.0030 100 80
% of FSR AIN Range = ± 2.5 V % of FSR AIN Range = ± 1.25 V µV Before Calibration n V /° C % Before Calibration ppm of FS/ C % of FSR Before Calibration ppm of FS/ C % of FSR After Calibration3 dB At DC, AIN = 1 V dB At DC, AIN = 1 V
737 24
15437
Hz Bits
Configure via Conversion Time Register FW 8 (Conversion Time 117 µs) See Typical Perfomance Charateristics
See Table IV See Tables V and VI ± 0.0015 ±1 ± 1.5 ± 0.2 ± 2.5 ± 0.2 ± 2.5 ± 0.0030 75 65
% of FSR mV Before Calibration µV/ C % Before Calibration ppm of FS/ C % of FSR Before Calibration ppm of FS/ C % of FSR After Calibration3 dB At DC, AIN = 1 V dB At DC, AIN = 1 V
2.9 0 1.45 0 725 0 0.2
± 2.5 0 to 2.5 ± 1.25 0 to 1.25 ± 625 0 to 625
+2.9 2.9 +1.45 1.45 +725 725 AVDD 0.3 200
200 2.475 2.5 0.5 2.525
V V V V mV mV V nA V V V µA
Only One Channel, Chop Disabled
NOREF Bit in Channel Status Register
0
A V DD 400 +1.05
1.05 FS 0.8 FS
2.1
FS V V FS V
2
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AD7738
Parameter LOGIC INPUTS SCLK, DIN, CS, and RESET Inputs Input Current Input Current CS Input Capacitance V T +1 VT1 VT+ VT1 V T +1 VT1 VT+ VT1 MCLK IN Only Input Current Input Capacitance VINL Input Low Voltage VINH Input High Voltage VINL Input Low Voltage VINH Input High Voltage LOGIC OUTPUTS MCLKOUT10, DOUT, RDY VOL Output Low Voltage VOH Output High Voltage VOL Output Low Voltage VOH Output High Voltage Floating State Leakage Current Floating State Leakage Capacitance P1 INPUT Input Current VINL Input Low Voltage VINH Input High Voltage P0, P1 OUTPUT VOL Output Low Voltage VOH Output High Voltage POWER REQUIREMENTS AVDD AGND Voltage DVDD DGND Voltage AVDD Current (Normal Mode) AVDD Current (Internal Buffer Off ) DVDD Current (Normal Mode)11 DVDD Current (Normal Mode)11 AVDD + DVDD Current (Standby Mode) 12 Power Dissipation (Normal Mode) 11 Power Dissipation (Standby Mode) 12 4.0 4.75 4.75 2.70 13.6 8.5 2.7 1.0 80 85 500 5.25 5.25 3.60 16 3 1.5 100 4 1.4 0.8 0.3 0.95 0.4 0.3 2 1.4 0.85 2 1.1 0.85 ± 10 4 0.8 3.5 0.4 2.5 Min Typ Max Unit Test Conditions/Comment
±1 ± 10 40
µA µA µA pF V V V V V V µA pF V V V V
CS = AVDD Internal Pull-Up Resistor D VDD = 5 V D V DD = 5 V D VDD = 5 V D VDD = 3 V D V DD = 3 V D VDD = 3 V
D V DD = 5 V D VDD = 5 V D V DD = 3 V D VDD = 3 V
0.4 4.0 0.4 DVDD 0.6 3 ± 10 0.8 3.5 0.4 0.4 0.4 ±1
V V V V µA pF µA V V V V V V V V V mA mA mA mA µA mW µW
ISINK = 800 µA, DVDD = 5 V ISOURCE = 200 µA, DVDD = 5 V ISINK = 100 µA, DVDD = 3 V ISOURCE = 100 µA, DVDD = 3 V
Levels Referenced to Analog Supplies A V DD = 5 V A V DD = 5 V ISINK = 8 mA, TMAX = 70°C, AVDD = 5 V ISINK = 5 mA, TMAX = 85°C, AVDD = 5 V ISINK = 2.5 mA, TMAX = 105°C, AVDD = 5 V ISOURCE = 200 µA, AVDD = 5 V
A V DD = 5 V A V DD = 5 V D VDD = 5 V D VDD = 3 V AVDD = DVDD = 5 V AVDD = DVDD = 5 V
NOTES 1 Specifications are not production tested, but guaranteed by design and/or characterization data at initial product release. 2 Specifications before calibration. Channel System Calibration reduces these errors to the order of the noise. 3 Applies after the Zero Scale and Full-Scale calibration. The Negative Full Scale error represents the remaining error after removing the offset and gain error. 4 Specifications before calibration. ADC Zero Scale Self-Calibration or Channel Zero Scale System Calibration reduces this error to the order of the noise. 5 The output data span corresponds to the Nominal (Typical) Input Voltage Range. Correct operation of the ADC is guaranteed within the specified min/max. Outside the Nominal Input Voltage Range, the OVR bit in the Channel Status register is set and the Channel Data register value depends on CLAMP bit in the Mode register. See the register description and circuit description for more details. 6 If chopping is enabled or when switching between channels, there will be a dynamic current charging the capacitance of the multiplexer, capacitance of the pins, and any additional capacitance connected to the MUXOUT. See the circuit description for more details. 7 For specified performance. Part is functional with Lower VREF 8 Dynamic current charging the sigma-delta modulator input switching capacitor. 9 Outside the specified calibration range, calibration is possible but the performance may degrade. 10 These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load. 11 With external MCLK, MCLKOUT disabled (CLKDIS bit set in the Mode register). 12 Exter nal MCLKIN = 0 V or DVDD, Digital Inputs = 0 V or DVDD, P0 and P1 = 0 V or AVDD. Specifications are subject to change without notice.
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AD7738 TIMING SPECIFICATIONS1, 2, 3
( A VD D = 5 V
Parameter MASTER CLOCK RANGE t1 t2 READ OPERATION t4 t5 4 t 5A 4, 5 t6 t7 t8 t9 6 WRITE OPERATION t11 t12 t13 t14 t15 t16 0 0 50 50 0 10 0 30 25 50 50 0 60 80 ns ns ns ns ns ns ns ns ns ns ns ns
5%; DVDD = 2.7 V to 3.6 V or 5 V
Min 1 50 500 0 0 0
5%; Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted.)
Max 6.144 Unit MHz ns ns ns 60 80 ns ns Test Conditions/Comment SYNC Pulsewidth RESET Pulsewidth CS Falling Edge to SCLK Falling Edge Setup Time SCLK Falling Edge to Data Valid Delay DVDD of 4.75 V to 5.25 V DVDD of 2.7 V to 3.3 V CS Falling Edge to Data Valid Delay DVDD of 4.75 V to 5.25 V DVDD of 2.7 V to 3.3 V SCLK High Pulsewidth SCLK Low Pulsewidth CS Rising Edge after SCLK Rising Edge Hold Time Bus Relinquish Time after SCLK Rising Edge CS Falling Edge to SCLK Falling Edge Setup Data Valid to SCLK Rising Edge Setup Time Data Valid after SCLK Rising Edge Hold Time SCLK High Pulsewidth SCLK Low Pulsewidth CS Rising Edge after SCLK Rising Edge Hold Time
Typ
80
NOTES 1 Sample tested during initial release to ensure compliance. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. 3 See Figures 1 and 2. 4 These numbers are measured with the load circuit of Figure 3 and defined as the time required for the output to cross the VOL or VOH limits. 5 This specification is relevant only if CS goes low while SCLK is low. 6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. Specifications are subject to change without notice.
4
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AD7738
CS
t4
SCLK
t6 t7 t9
MSB LSB
t8
t5 t5A
DOUT
Figure 1. Read Cycle Timing Diagram
CS
t11
SCLK
t14
t16
t12 t13
DIN MSB
t15
LSB
Figure 2. Write Cycle Timing Diagram
ISINK (800 A AT DVDD = 5V 100 A AT DVDD = 3V) TO OUTPUT PIN 50pF
1.6V
ISOURCE ( 200 A AT DVDD = 5V 100 A AT DVDD = 3V)
Figure 3. Load Circuit for Access Time and Bus Relinquish Time
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