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Details, datasheet, quote on part number:AD7808P
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Datasheet text preview:
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FEATURES Four 10-Bit DACs in One Package Serial and Parallel Loading Facilities Available AD7804 Quad 10-Bit Serial Loading AD7805 Quad 10-Bit Parallel Loading AD7808 Octal 10-Bit Serial Loading AD7809 Octal 10-Bit Parallel Loading +3.3 V to +5 V Operation Power-Down Mode Power-On Reset Standby Mode (All DACs/Individual DACs) Low Power All CMOS Construction 10-Bit Resolution Double Buffered DAC Registers Dual External Reference Capability APPLICATIONS Optical Disk Drives Instrumentation and Communication Systems Process Control and Voltage Setpoint Control Trim Potentiometer Replacement Automatic Calibration GENERAL DESCRIPTION
+3.3 V to +5 V Quad/Octal 10-Bit DACs AD7804/AD7805/AD7808/AD7809*
FUNCTIONAL BLOCK DIAGRAMS
AVDD DVDD REFOUT REFIN AVDD DIVIDER COMP CHANNEL D CONTROL REG DATA REGISTER VBIAS DAC C DAC REGISTER MUX 1.23V REF AGND DGND VOUTF* POWER ON RESET
AD7804/ AD7808
VBIAS DAC D
VOUTE*
VOUTD
MUX
VOUTC
CHANNEL C CONTROL REG
DATA REGISTER VBIAS MUX
DAC REGISTER
DAC B
VOUTB
CHANNEL B CONTROL REG
DATA REGISTER VBIAS
DAC REGISTER
MUX
DAC A
VOUTA
PD**
CHANNEL A CONTROL REG SYSTEM CONTROL REG
DATA REGISTER
DAC REGISTER VOUTH*
The AD7804/AD7808 are quad/octal 10-bit digital-to-analog converters, with serial load capabilities, while the AD7805/AD7809 are quad/octal 10-bit digital-to-analog converters with parallel load capabilities. These parts operate from a +3.3 V to +5 V (± 10%) power supply and incorporates an on-chip reference. These DACs provide output signals in the form of VBIAS ± VSWING. VSWING is derived internally from VBIAS. On-chip control registers include a system control register and channel control registers. The system control register has control over all DACs in the package. The channel control registers allow individual control of DACs. The complete transfer function of each individual DAC can be shifted around the VBIAS point using an on-chip Sub DAC. All DACs contain double buffered data inputs, which allow all analog outputs to be simultaneously updated using the asynchronous LDAC input.
Control Features S Hardware Clear ystem Control Power Down1 S System Standby2 I ystem Clear C put Coding n hannel Control C Channel Standby2 V hannel Clear NB I A S
1
FSIN CLKIN SDIN
INPUT SHIFT REGISTER & CONTROL LOGIC
VOUTG*
CLR LDAC **ONLY AD7804 SHOWN FOR CLARITY **SHOWS ADDITIONAL CHANNELS ON THE AD7808 **PIN ON THE AD7808 ONLY
AVDD DVDD REFOUT REFIN AVDD DIVIDER COMP CHANNEL D CONTROL REG 1.23V REF
AGND DGND VOUTF*
POWER ON RESET
AD7805/ AD7809
VBIAS DAC D
VOUTE*
MUX
VOUTD
DATA REGISTER VBIAS
DAC REGISTER
MUX
DAC C
VOUTC
CHANNEL C CONTROL REG
DATA REGISTER VBIAS MUX
DAC REGISTER
DAC B
VOUTB
Channels Controlled All All All All All Selective Selective Selective
Main DAC
Sub DAC
CHANNEL B CONTROL REG DATA REGISTER VBIAS MUX DAC A VOUTA DAC REGISTER
PD**
CHANNEL A CONTROL REG SYSTEM CONTROL REG
DATA REGISTER
DAC REGISTER
VOUTH* INPUT REGISTER VOUTG*
CS WR
CONTROL LOGIC
OTES Power-down function powers down all internal circuitry including the reference. 2 Standby functions power down all circuitry except for the reference.
MODE A0 A1 A2** DB9 DB2 DB1 DB0 CLR LDAC **ONLY AD7805 SHOWN FOR CLARITY **SHOWS ADDITIONAL CHANNELS ON THE AD7809 **PIN ON THE AD7809 ONLY
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
*Patent pending. Index on Page 26.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998
AD7804/AD7805/AD7808/AD7809
AD7804/AD7805SPECIFICATIONS (AV
Reference = Internal Reference; CL = 100 pF; RL = 2 k
Parameter STATIC PERFORMANCE MAIN DAC Resolution Relative Accuracy Gain Error Bias Offset Error2 Zero-Scale Error3 Monotonicity Minimum Load Resistance SUB DAC Resolution Differential Nonlinearity OUTPUT CHARACTERISTICS Output Voltage Range3 Voltage Output Settling Time to 10 Bits Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough Digital Crosstalk Analog Crosstalk DC Output Impedance Power Supply Rejection Ratio DAC REFERENCE INPUTS REF IN Range REF IN Input Leakage DIGITAL INPUTS Input High Voltage, VIH @ VDD = 5 V Input High Voltage, VIH @ VDD = 3.3 V Input Low Voltage, VIL @ VDD = 5 V Input Low Voltage, VIL @ VDD = 3.3 V Input Leakage Current Input Capacitance Input Coding REFERENCE OUTPUT REF OUT Output Voltage REF OUT Error REF OUT Temperature Coefficient REF OUT Output Impedance POWER REQUIREMENTS VDD (AVDD and DVDD) IDD (AIDD Plus DIDD) Normal Mode System Standby (SSTBY) Mode Power-Down (PD) Mode @ +25°C TMINTMAX Power Dissipation Normal Mode System Standby (SSTBY) Mode Power-Down (PD) Mode @ +25°C TMINTMAX B Grade1 C Grade1 10 ±3 ±3 80/+40 V BIAS / +40 16 9 2 8 ± 0.125 ± 0.5 VBIAS ± 15/16 × VBIAS VBIAS /16 to 31/16 × VBIAS 4 2.5 1 0.5 0.5 ± 0.2 2 0.002 1.0 to VDD/2 ±1 2.4 2.1 0.8 0.6 ± 10 10 Twos Comp/Binary 1.23 ±8 100 5 3/5.5 12 250 0.8 1.5 66 1.38 4.4 8.25 10 ±3 ±3 80/+40 V BIAS / +40 16 10 2 8 ± 0.125 ± 0.5
10% to 5 V 10%; AGND = DGND = 0 V; DD and DV DD = 3.3 V to GND. Sub DAC at Midscale. All specifications TMIN to TMAX unless otherwise noted.)
Units Comments
Bits LSB max % FSR max mV max mV max Bits k min Bits LSB typ LSB max V V µs max V/µs typ nV-s typ nV-s typ nV-s typ LSB typ typ %/% typ V min to V max µA max V min V min V max V max pF max
DAC Code = 0.5 Full Scale DAC Code = 000H for Offset Binary and 200H for Twos Complement Coding
Refers to an LSB of the Main DAC
VBIAS ± 15/16 × VBIAS VBIAS/16 to 31/16 × VBIAS 4 2.5 1 0.5 0.5 ± 0.2 2 0.002 1.0 to VDD/2 ±1 2.4 2.1 0.8 0.6 µA max 10 Twos Comp/Binary 1.23 ±8 100 5 3/5.5 12 250 0.8 1.5 66 1.38 4.4 8.25
Twos Complement Coding Offset Binary Coding Typically 1.5 µs 1 LSB Change Around the Major Carry
VDD ± 10%
Typically ± 1 nA
V nom % max ppm/°C typ k nom V min to V max mA max µA µA max µA max mW max mW max µW max µW max Excluding Load Currents VIH = V DD, V IL = DGND VIH = V DD, V IL = DGND VIH = V DD, V IL = DGND Excluding Power Dissipated in Load
NOTES 1 Temperature range is 40°C to +85°C. 2 Can be minimized using the Sub DAC. 3 VBIAS is the center of the output voltage swing and can be V DD/2, Internal Reference or REFIN as determined by MX1 and MX0 in the channel control register. Specifications subject to change without notice.
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REV. A
AD7804/AD7805/AD7808/AD7809
AD7808/AD7809SPECIFICATIONS (AV
Reference = Internal Reference; CL = 100 pF; RL = 2 k
Parameter STATIC PERFORMANCE MAIN DAC Resolution Relative Accuracy Gain Error Bias Offset Error2 Zero-Scale Error Monotonicity Minimum Load Resistance SUB DAC Resolution Differential Nonlinearity OUTPUT CHARACTERISTICS Output Voltage Range3 Voltage Output Settling Time to 10 Bits Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough Digital Crosstalk Analog Crosstalk DC Output Impedance Power Supply Rejection Ratio DAC REFERENCE INPUTS REF IN Range REF IN Input Leakage DIGITAL INPUTS Input High Voltage, VIH @ VDD = 5 V Input High Voltage, VIH @ VDD = 3.3 V Input Low Voltage, VIL @ VDD = 5 V Input Low Voltage, VIL @ VDD = 3.3 V Input Leakage Current Input Capacitance Input Coding REFERENCE OUTPUT REF OUT Output Voltage REF OUT Error REF OUT Temperature Coefficient REF OUT Output Impedance POWER REQUIREMENTS VDD (AVDD and DVDD) IDD (AIDD Plus DIDD) Normal Mode System Standby (SSTBY) Mode Power-Down (PD) Mode @ +25°C TMINTMAX Power Dissipation Normal Mode System Standby (SSTBY) Mode Power-Down (PD) Mode @ +25°C TMINTMAX B Grade1 10 ±4 ±3 ± 60 ± 35 9 2 8 ± 0.125 ± 0.5 VBIAS ± 15/16 × VBIAS VBIAS /16 to 31/16 × VBIAS 4 2.5 1 0.5 0.5 ± 0.2 2 0.002 1.0 to VDD/2 ±1 2.4 2.1 0.8 0.6 ± 10 8 Twos Comp/Binary 1.23 ±8 100 5 3/5.5 18 250 1 3 99 1.38 5.5 16.5
10% to 5 V 10%; AGND = DGND = 0 V; DD and DV DD = 3.3 V to GND. Sub DAC at Midscale. All specifications TMIN to TMAX unless otherwise noted.)
Units Comments
Bits LSB max % FSR max mV max mV max Bits k min Bits LSB typ LSB max V V µs max V/µs typ nV-s typ nV-s typ nV-s typ LSB typ typ %/% typ V min to V max µA max V min V min V max V max µA max pF max
DAC Code = 0.5 Full Scale DAC Code = 000H for Offset Binary and 200H for Twos Complement Coding
Refers to an LSB of the Main DAC
Twos Complement Coding Offset Binary Coding Typically 1.5 µs 1 LSB Change Around the Major Carry
VDD ± 10%
Typically ± 1 nA
V nom % max ppm/°C typ k nom V min to V max mA max µA max µA max µA max mW max mW max µW max µW max Excluding Load Currents VIH = V DD, V IL = DGND VIH = VDD , VIL = DGND VIH = V DD, V IL = DGND Excluding Power Dissipated in Load
NOTES 1 Temperature range is 40°C to +85°C. 2 Can be minimized using the Sub DAC. 3 VBIAS is the center of the output voltage swing and can be V DD/2, Internal Reference or REFIN as determined by MX1 and MX0 in the channel control register. Specifications subject to change without notice.
REV. A
3
AD7804/AD7805/AD7808/AD7809 AD7804/AD7808 TIMING CHARACTERISTICS1(V
Internal Reference. All specifications TMIN to TMAX unless otherwise noted.)
Parameter t1 t2 t3 t4 t5 t6 t6A t7 t8 t9 Limit at TMIN, T MAX All Versions 100 40 40 30 30 5 6 90 20 40 100 Units ns min ns min ns min ns min ns min ns min ns min ns max ns min ns min ns min Description CLKIN Cycle Time CLKIN High Time CLKIN Low Time FSIN Setup Time Data Setup Time Data Hold Time LDAC Hold Time FSIN Hold Time LDAC, CLR Pulsewidth LDAC Setup Time
DD =
3.3 V
10% to 5 V
10%; AGND = DGND = 0 V; Reference =
NOTES 1 Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and timed from a voltage of (V IL + VIH)/2. Specifications subject to change without notice.
t1
CLKIN(I)
t2 t4
FSIN(I)
t3 t7
t5 t6
SDIN(I) DB15 DB0
t5
LDAC1
t6A
LDAC2
t9
t8
CLR
t8
1TIMING REQUIREMENTS FOR SYNCHRONOUS LDAC UPDATE OR LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED. 2TIMING REQUIREMENTS FOR ASYNCHRONOUS LDAC UPDATE.
Figure 1. Timing Diagram for AD7804 and AD7808
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REV. A
AD7804/AD7805/AD7808/AD7809
(VDD = 3.3 V = Internal Reference. All specifications TMIN to TMAX unless otherwise noted.)
Parameter t1 t2 t3 t4 t5 t6 t6A t7 t8 t9 t10 t11 t12 Limit at TMIN, T MAX All Versions 25 4.5 25 4.5 25 4.5 6 40 0 40 100 40 100 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min
AD7805/AD7809 TIMING CHARACTERISTICS1
10% to 5 V
10%; AGND = DGND = 0 V; Reference
Description Mode Valid to Write Setup Time Mode Valid to Write Hold Time Address Valid to Write Setup Time Address Valid to Write Hold Time Data Setup Time Data Hold Time LDAC Valid to Write Hold Time Chip Select to Write Setup Time Chip Select to Write Hold Time Write Pulsewidth Time Between Successive Writes LDAC, CLR Pulsewidth Write to LDAC Setup Time
NOTE 1 Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and timed from a voltage of (V IL + VIH)/2. Specifications subject to change without notice.
t1
MODE
t2
t3
A0, A1, A2
t4
CS
t7
t8
t10 t9
WR
t5
DATA
t6
t6A
LDAC 1
t12
LDAC 2
t11
t11
CLR
1TIMING REQUIREMENTS FOR SYNCHRONOUS LDAC UPDATE OR LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED. 2TIMING REQUIREMENTS FOR ASYNCHRONOUS LDAC UPDATE.
Figure 2. Timing Diagram for AD7805/AD7809 Parallel Write
REV. A
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