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Details, datasheet, quote on part number:AD7810YR
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Datasheet text preview:
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FEATURES 10-Bit ADC with 2.3 s Conversion Time Small Footprint 8-Lead microSOIC Package Specified Over a 40 C to +105 C Temperature Range Inherent Track-and-Hold Functionality Operating Supply Range: 2.7 V to 5.5 V Specifications at 2.7 V to 5.5 V Microcontroller-Compatible Serial Interface Optional Automatic Power-Down at End of Conversion Low Power Operation 270 W at 10 kSPS Throughput Rate 2.7 mW at 100 kSPS Throughput Rate Analog Input Range: 0 V to VREF Reference Input Range: 0 V to V DD APPLICATIONS Low Power, Hand-Held Portable Applications that Require Analog-to-Digital Conversion with 10-Bit Accuracy; e.g., Battery Powered Test Equipment, Battery-Powered Communications Systems
2.7 V to 5.5 V, 2.3 s, 10-Bit ADC in 8-Lead microSOIC/DIP AD7810
FUNCTIONAL BLOCK DIAGRAM
VDD AGND VREF
AD7810
CHARGE REDISTRIBUTION DAC CLOCK OSC
SERIAL PORT
DOUT SCLK
VIN+ VIN COMP VDD/3 CONTROL LOGIC
CONVST
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7810 is a high speed, low power, 10-bit A/D converter that operates from a single 2.7 V to 5.5 V supply. The part contains a 2.3 µs successive approximation A/D converter, with inherent track/hold functionality, a pseudo differential input and a high speed serial interface that interfaces to most microcontrollers. The AD7810 is fully specified over a temperature range of 40°C to +105°C. By using a technique that samples the state of the CONVST (convert start) signal at the end of a conversion, the AD7810 may be used in an automatic power-down mode. When used in this mode, the AD7810 automatically powers down at the end of a conversion and "wakes up" at the start of a new conversion. This feature significantly reduces the power consumption of the part at lower throughput rates. The AD7810 can also operate in a high speed mode where the part is not powered down between conversions. In this high speed mode of operation, the conversion time of the AD7810 is 2.3 µs. The maximum throughput rate is dependent on the speed of the serial interface of the microcontroller. The part is available in a small 8-lead, 0.3" wide, plastic dualin-line package (mini-DIP); in an 8-lead, small outline IC (SOIC); and in an 8-lead microSOIC package.
1. Complete, 10-Bit ADC in 8-Lead Package The AD7810 is a 10-bit 2.3 µs ADC with inherent track/hold functionality and a high speed serial interface--all in an 8-lead microSOIC package. VREF may be connected to VDD to eliminate the need for an external reference. The result is a high speed, low power, space saving ADC solution. 2. Low Power, Single Supply Operation The AD7810 operates from a single 2.7 V to 5.5 V supply and typically consumes only 9 mW of power while converting. The power dissipation can be significantly reduced at lower throughput rates by using the automatic power-down mode, e.g., at a throughput rate of 10 kSPS the power consumption is only 270 µW. 3. Automatic Power-Down The automatic power-down mode, whereby the AD7810 powers down at the end of a conversion and "wakes up" before the next conversion, means the AD7810 is ideal for battery powered applications. See Power vs. Throughput Rate section. 4. Serial Interface An easy to use, fast serial interface allows connection to most popular microprocessors with no external circuitry.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000
AD7810SPECIFICATIONS (GND = 0 V, V
Parameter DYNAMIC PERFORMANCE Signal to (Noise + Distortion) Ratio1 Total Harmonic Distortion1 Peak Harmonic or Spurious Noise Intermodulation Distortion2 2nd Order Terms 3rd Order Terms DC ACCURACY Resolution Relative Accuracy1 Differential Nonlinearity (DNL)1 Offset Error1 Gain Error1 Minimum Resolution for Which No Missing Codes Are Guaranteed ANALOG INPUT Input Voltage Range Input Leakage Current2 Input Capacitance2 REFERENCE INPUTS2 VREF Input Voltage Range Input Leakage Current Input Capacitance LOGIC INPUTS2 VINH, Input High Voltage VINL, Input Low Voltage Input Current, IIN Input Capacitance, CIN LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL High Impedance Leakage Current High Impedance Capacitance CONVERSION RATE Conversion Time Track/Hold Acquisition Time1 POWER SUPPLY V DD IDD Power Dissipation Power-Down Mode IDD Power Dissipation Automatic Power Down 1 kSPS Throughput 10 kSPS Throughput 100 kSPS Throughput 58 64 64 67 67 10 ±1 ±1 ±2 ±2 10 0 V REF ±1 15 1.2 V DD ±3 20 2.0 0.4 ±1 8 2.4 0.4 ± 10 15 2.3 100 2.75.5 3.5 17.5 1 5 27 270 2.7
REF
= VDD. All specifications 40 C to +105 C unless otherwise noted.)
Unit dB min dB max dB max fa = 48 kHz, fb = 48.5 kHz dB typ dB typ Bits LSB max LSB max LSB max LSB max Bits V min V max µA max pF max V min V max µA max pF max V min V max µA max pF max V min V max µA max pF max µs max ns max Volts mA max mW max µA max µW max µW max µW max mW max Test Conditions/Comments fIN = 30 kHz, fSAMPLE = 350 kHz
Y Version
Typically 10 nA, VIN = 0 V to VDD
ISOURCE = 200 µA ISINK = 200 µA
See DC Acquisition Time Section For Specified Performance Sampling at 350 kSPS and Logic Inputs at VDD or 0 V. VDD = 5 V VDD = 5 V; VDD = 3 V
NOTES 1 See Terminology section. 2 Sample tested during initial release and after any redesign or process change that may affect this parameter. Specifications subject to change without notice.
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AD7810 Timing Characteristics1, 2 (40 C to +105 C, V
Parameter t1 t2 t3 t4 t5 3 t6 3 t7 3 t 8 3, 4 tPOWER UP VDD = 5 V 2.3 20 25 25 5 10 5 20 10 1.5 10% VDD = 3 V 2.3 20 25 25 5 10 5 20 10 1.5 10%
REF
= VDD, unless otherwise noted)
Conditions/Comments Conversion Time Mode 1 Operation (High Speed Mode) CONVST Pulsewidth SCLK High Pulsewidth SCLK Low Pulsewidth CONVST Rising Edge to SCLK Rising Edge Set-Up Time SCLK Rising Edge to DOUT Data Valid Delay Data Hold Time after Rising Edge SCLK Bus Relinquish Time after Falling Edge of SCLK Power-Up Time after Rising Edge of CONVST
Unit µs (max) ns (min) ns (min) ns (min) ns (min) ns (max) ns (max) ns (max) ns (min) µs (max)
NOTES 1 Sample tested to ensure compliance. 2 See Figures 14, 15 and 16. 3 These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V DD = 5 V ± 10% and 0.4 V or 2 V for V DD = 3 V ± 10%. 4 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the Timing Characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V Digital Input Voltage to GND (CONVST, SCLK) . . . . . . . . . . . . . . 0.3 V, VDD + 0.3 V Digital Output Voltage to GND (DOUT) . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, VDD + 0.3 V VREF to GND . . . . . . . . . . . . . . . . . . . . . . 0.3 V, VDD + 0.3 V Analog Inputs (VIN+, VIN) . . . . . . . . . . . . . . . . . . . . 0.3 V, VDD + 0.3 V Storage Temperature Range . . . . . . . . . . . . 65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 125°C/W JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 50°C/W Lead Temperature Soldering (10 sec) . . . . . . . . . . . 260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 160°C/W JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 56°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C MicroSOIC Package, Power Dissipation . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/W JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD7810YN AD7810YR AD7810YRM
Linearity Error (LSB) ± 1 LSB ± 1 LSB ± 1 LSB
Temperature Range 40°C to +105°C 40°C to +105°C 40°C to +105°C
Package Description Plastic DIP Small Outline IC (SOIC) microSOIC
Package Options N-8 SO-8 RM-8
Branding Information
C1Y
IOL 200 A TO OUTPUT PIN 1.6V CL 50pF IOH 200 A
Figure 1. Load Circuit for Digital Output Timing Specifications
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AD7810
PIN FUNCTION DESCRIPTIONS
Pin No. 1
Mnemonic CONVST
Description Convert Start. Falling edge puts the track-and-hold into hold mode and initiates a conversion. A rising edge on the CONVST pin enables the serial port of the AD7810. This is useful in multipackage applications where a number of devices share the same serial bus. The state of this pin at the end of conversion also determines whether the part is powered down or not. See Operating Modes section of this data sheet. Positive input of the pseudo differential analog input. Negative input of the pseudo differential analog input. Ground reference for analog and digital circuitry. External reference is connected here. Serial data is shifted out on this pin. Serial Clock. An external serial clock is applied here. Positive Supply Voltage 2.7 V to 5.5 V.
2 3 4 5 6 7 8
VIN+ V IN GND V REF D OUT SCLK VDD
PIN CONFIGURATION DIP/SOIC
CONVST 1 VIN+ 2 8 VDD
7 SCLK TOP VIEW VIN 3 (Not to Scale) 6 DOUT 5 VREF
AD7810
GND 4
Typical Performance Characteristics
10
15
1
35 dBs
2048 POINT FFT SAMPLING 357.142kSPS FIN = 30kHz
POWER mW
55
0.1
75
95
10
30 20 THROUGHPUT kSPS
40
50
Figure 2. Power vs. Throughput
4
1 23 45 67 89 111 133 155 177 199 221 243 265 287 309 331 353 375 397 419 441 463 485 507 529 551 573 595 617 639 661 683 705 727 749 771 793 815 837 859 881 903 925 947 969 991 1013
0.01 0
115
FREQUENCY BINS
Figure 3. AD7810 SNR
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AD7810
TERMINOLOGY Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02N + 1.76) dB Thus for a 10-bit converter, this is 62 dB.
Total Harmonic Distortion
The AD7810 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second and third order terms are of different significance. The second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs.
Relative Accuracy
Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7810 it is defined as:
THD ( dB ) = 20 log
2 2 2 2 V2 + V 3 + V 4 + V 5
Relative accuracy or endpoint nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function.
Differential Nonlinearity
V1
This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.
Offset Error
where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V62 are the rms amplitudes of the second through the sixth harmonics.
Peak Harmonic or Spurious Noise
This is the deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Gain Error
Peak harmonic or spurious noise is defined as the ratio of the rms values of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak.
Intermodulation Distortion
This is the deviation of the last code transition (1111 . . . 110) to (1111 . . . 111) from the ideal (i.e., VREF 1 LSB) after the offset error has been adjusted out.
Track/Hold Acquisition Time
With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa fb), while the third order terms include (2fa + fb), (2fa fb), (fa + 2fb) and (fa 2fb).
Track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within ±1/2 LSB, after the end of conversion (the point at which the track/hold returns to track mode). It also applies to situations where there is a step input change on the input voltage applied to the VIN+ input of the AD7810. It means that the user must wait for the duration of the track/hold acquisition time, after the end of conversion or after a step input change to VIN+, before starting another conversion to ensure that the part operates to specification.
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