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Details, datasheet, quote on part number:AD7811YRU
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Datasheet text preview:
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FEATURES 10-Bit ADC with 2.3 s Conversion Time The AD7811 has Four Single-Ended Inputs that Can Be Configured as Three Pseudo Differential Inputs with Respect to a Common, or as Two Independent Pseudo Differential Channels The AD7812 has Eight Single-Ended Inputs that Can Be Configured as Seven Pseudo Differential Inputs with Respect to a Common, or as Four Independent Pseudo Differential Channels Onboard Track and Hold Onboard Reference 2.5 V 2.5% Operating Supply Range: 2.7 V to 5.5 V Specifications at 2.7 V3.6 V and 5 V 10% DSP-/Microcontroller-Compatible Serial Interface High Speed Sampling and Automatic Power-Down Modes Package Address Pin on the AD7811 and AD7812 Allows Sharing of the Serial Bus in Multipackage Applications Input Signal Range: 0 V to VREF Reference Input Range: 1.2 V to VDD GENERAL DESCRIPTION
2.7 V to 5.5 V, 350 kSPS, 10-Bit 4-/8-Channel Sampling ADCs AD7811/AD7812
The control registers of the AD7811 and AD7812 allow the input channels to be configured as single-ended or pseudo differential. The control register also features a software convert start and a software power-down. Two of these devices can share the same serial bus and may be individually addressed in a multipackage application by hardwiring the device address pin. The AD7811 is available in a small, 16-lead 0.3" wide, plastic dual-in-line package (mini-DIP), in a 16-lead 0.15" wide, Small Outline IC (SOIC) and in a 16-lead, Thin Shrink Small Outline Package (TSSOP). The AD7812 is available in a small, 20-lead 0.3" wide, plastic dual-in-line package (mini-DIP), in a 20-lead, Small Outline IC (SOIC) and in a 20-lead, Thin Shrink Small Outline Package (TSSOP).
PRODUCT HIGHLIGHTS
The AD7811 and AD7812 are high speed, low power, 10-bit A/D converters that operate from a single 2.7 V to 5.5 V supply. The devices contain a 2.3 µs successive approximation A/D converter, an on-chip track/hold amplifier, a 2.5 V on-chip reference and a high speed serial interface that is compatible with the serial interfaces of most DSPs (Digital Signal Processors) and microcontrollers. The user also has the option of using an external reference by connecting it to the VREF pin and setting the EXTREF bit in the control register. The VREF pin may be tied to VDD. At slower throughput rates the power-down mode may be used to automatically power down between conversions.
1. Low Power, Single Supply Operation Both the AD7811 and AD7812 operate from a single 2.7 V to 5.5 V supply and typically consume only 10 mW of power. The power dissipation can be significantly reduced at lower throughput rates by using the automatic powerdown mode e.g., 315 µW @ 10 kSPS, VDD = 3 V--see Power vs. Throughput. 2. 4-/8-Channel, 10-Bit ADC The AD7811 and AD7812 have four and eight single-ended input channels respectively. These inputs can be configured as pseudo differential inputs by using the Control Register. 3. On-chip 2.5 V (± 2.5%) reference circuit that is powered down when using an external reference. 4. Hardware and Software Control The AD7811 and AD7812 provide for both hardware and software control of Convert Start and Power-Down.
FUNCTIONAL BLOCK DIAGRAMS
CREF 1.23V REF BUF CLOCK OSC CHARGE REDISTRIBUTION DAC VIN1 VIN2 VIN3 VIN4 SERIAL PORT REFIN VDD AGND DGND CREF 1.23V REF CLOCK OSC CHARGE REDISTRIBUTION DAC MUX CONTROL LOGIC SERIAL PORT REFIN VDD AGND DGND
AD7811
DOUT DIN RFS TFS SCLK VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8
AD7812
DOUT DIN RFS TFS SCLK
BUF
MUX VDD / 3 COMP
CONTROL LOGIC
VDD / 3
COMP
A0 CONVST
A0 CONVST
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000
AD7811/AD7812SPECIFICATIONS [EXT]. All specifications 40 C to +105 C unless otherwise noted.)
Parameter DYNAMIC PERFORMANCE Signal to (Noise + Distortion) Ratio1 Total Harmonic Distortion (THD)1 Peak Harmonic or Spurious Noise1 Intermodulation Distortion1, 2 Second Order Terms Third Order Terms Channel-to-Channel Isolation1, 2 DC ACCURACY Resolution Minimum Resolution for Which No Missing Codes are Guaranteed Relative Accuracy1 Differential Nonlinearity1 Gain Error1 Gain Error Match1 Offset Error1 Offset Error Match1 ANALOG INPUT Input Voltage Range Input Leakage Current2 Input Capacitance2 REFERENCE INPUTS2 VREF Input Voltage Range Input Leakage Current Input Capacitance ON-CHIP REFERENCE Reference Error Temperature Coefficient LOGIC INPUTS2 VINH, Input High Voltage VINL, Input Low Voltage VINH, Input High Voltage VINL, Input Low Voltage Input Current, IIN Input Capacitance, CIN LOGIC OUTPUTS Output High Voltage, VOH 4 2.4 Output Low Voltage, VOL High Impedance Leakage Current High Impedance Capacitance CONVERSION RATE Conversion time Track/Hold Acquisition Time1 0.4 ±1 15 2.3 200 V max µA max pF max µs max ns max V min V min Y Version 58 66 80 67 67 80 10 10 ±1 ±1 ±2 ± 0.75 ±2 ± 0.75 0 V REF ±1 20 1.2 V DD ±3 20 ± 2.5 50 2.4 0.8 2 0.4 ±1 8 Unit dB min dB max dB typ dB max dB max dB typ Bits Bits LSB max LSB max LSB max LSB max LSB max LSB max V min V max µA max pF max V min V max µA max pF max Nominal 2.5 V % max ppm/°C typ V min V max V min V max µA max pF max VDD = 5 V ± 10% VDD = 5 V ± 10% VDD = 3 V ± 10% VDD = 3 V ± 10% Typically 10 nA, VIN = 0 V to VDD Test Conditions/Comments fIN = 30 kHz Any Channel, fSAMPLE = 350 kHz VREF Internal or External fa = 29 kHz, fb = 30 kHz
(VDD = 2.7 V to 3.6 V, VDD = 5 V
10%, GND = 0 V, VREF = VDD
fIN = 20 kHz Any Channel
ISOURCE = 200 µA VDD = 5 V ± 10% VDD = 3 V ± 10% ISINK = 200 µA
2
REV. B
AD7811/AD7812
Parameter POWER SUPPLY V DD IDD Normal Operation Power-Down Full Power-Down Partial Power-Down (Internal Ref) Power Dissipation Normal Operation Auto Full Power-Down Throughput 1 kSPS Throughput 10 kSPS Throughput 100 kSPS Partial Power-Down (Internal Ref) Full Power-Down Y Version 2.7 5.5 3.5 1 350 10.5 31.5 315 3.15 1.05 3 Unit V min V max mA max µA max µA max mW max See Power vs. Throughput Section µW max µW max mW max mW max µW max Test Conditions/Comments For Specified Performance Digital Inputs = 0 V or VDD
See Power-Up Times Section V DD = 3 V
NOTES 1 See Terminology. 2 Sample tested during initial release and after any redesign or process change that may affect this parameter. Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2 (V
Parameter tP O W E R - U P t1 t2 t3 t4 t5 3 t6 3 t7 3 t8 t9 t1 0 3 , 4 t1 1 Y Version 1.5 2.3 20 25 25 5 5 10 10 5 20 100 Unit
DD
= 2.7 V to 5.5 V, VREF = VDD [EXT] unless otherwise noted)
Conditions/Comments Power-Up Time of AD7811/AD7812 after Rising Edge of CONVST Conversion Time CONVST Pulsewidth SCLK High Pulsewidth SCLK Low Pulsewidth RFS Rising Edge to SCLK Rising Edge Setup Time TFS Falling Edge to SCLK Falling Edge Setup Time SCLK Rising Edge to Data Out Valid DIN Data Valid to SCLK Falling Edge Setup Time DIN Data Valid after SCLK Falling Edge Hold Time SCLK Rising Edge to DOUT High Impedance DOUT High Impedance to CONVST Falling Edge
µs (max) µs (max) ns (min) ns (min) ns (min) ns (min) ns (min) ns (max) ns (min) ns (min) ns (max) ns (min)
NOTES 1 Sample tested to ensure compliance. 2 See Figures 16, 17 and 18. 3 These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V DD = 5 V ± 10% and 0.4 V or 2 V for V DD = 3 V ± 10%. 4 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 11, quoted in the Timing Characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances. Specifications subject to change without notice.
200 A
IOL
TO OUTPUT PIN
2.1V CL 50pF 200 A IOH
Figure 1. Load Circuit for Digital Output Timing Specifications
REV. B
3
AD7811/AD7812
ABSOLUTE MAXIMUM RATINGS*
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V Digital Input Voltage to DGND (CONVST, SCLK, RFS, TFS, DIN, A0) . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, VDD + 0.3 V Digital Output Voltage to DGND (DOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, VDD + 0.3 V REFIN to AGND . . . . . . . . . . . . . . . . . . . 0.3 V, VDD + 0.3 V Analog Inputs VIN1VIN4 (AD7811) . . . . . . . . . . . . . . 0.3 V, VDD + 0.3 V VIN1VIN8 (AD7812) . . . . . . . . . . . . . . 0.3 V, VDD + 0.3 V Storage Temperature Range . . . . . . . . . . . . 65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W Lead Temperature, (Soldering 10 sec) . . . . . . . . . . . . 260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 75°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 115°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD7811YN AD7811YR AD7811YRU AD7812YN AD7812YR AD7812YRU
Linearity Error ± 1 LSB ± 1 LSB ± 1 LSB ± 1 LSB ± 1 LSB ± 1 LSB
Package Descriptions 16-Lead Plastic DIP 16-Lead Small Outline IC (SOIC) 16-Lead Thin Shrink Small Outline Package (TSSOP) 20-Lead Plastic DIP 20-Lead Small Outline IC (SOIC) 20-Lead Thin Shrink Small Outline Package (TSSOP)
Package Options N-16 R-16A RU-16 N-20 R-20A RU-20
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7811/AD7812 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
4
REV. B
AD7811/AD7812
PIN CONFIGURATIONS DIP/SOIC/TSSOP
VREF CREF VIN1
1 2 3
16 VDD 15 CONVST 14 SCLK
VREF 1 CREF VIN1 AGND VIN2 VIN3 VIN4 VIN5 VIN6 2 3 4 5 6
20 VDD 19 CONVST 18 SCLK 17 DIN
AGND 4 VIN2 VIN3 VIN4 A0
AD7811
13 DIN
TOP VIEW 5 (Not to Scale) 12 DOUT 6 7 8 11 RFS 10 TFS 9 DGND
16 DOUT TOP VIEW 15 RFS (Not to Scale) 14 TFS 7 13 DGND 12 A0 11 VIN8
AD7812
8 9
VIN7 10
PIN FUNCTION DESCRIPTIONS
Pin(s) AD7811 1
Pin(s) AD7812 1
Mnemonic V REF
Description An external reference input can be applied here. When using an external precision reference or VDD the EXTREF bit in the control register must be set to logic one. The external reference input range is 1.2 V to VDD. Reference Capacitor. A capacitor (10 nF) is connected here to improve the noise performance of the on-chip reference. Analog Inputs. The analog input range is 0 V to VREF. Analog Ground. Ground reference for track/hold, comparator, on-chip reference and DAC. Package Address Pin. This Logic Input can be hardwired high or low. When used in conjunction with the package address bit in the control register this input allows two devices to share the same serial bus. For example a twelve channel solution can be achieved by using the AD7811 and the AD7812 on the same serial bus. Digital Ground. Ground reference for digital circuitry. Transmit Frame Sync. The falling edge of this Logic Input tells the part that a new control byte should be shifted in on the next 10 falling edges of SCLK. Receive Frame Sync. The rising edge of this Logic Input is used to enable a counter in the serial interface. It is used to provide compatibility with DSPs which use a continuous serial clock and framing signal. In multipackage applications the RFS Pin can also be used as a serial bus select pin. The serial interface will ignore the SCLK until it receives a rising edge on this input. The counter is reset at the end of a serial read operation. Serial Data Output. Serial data is shifted out on this pin on the rising edge of the serial clock. The output enters a High impedance condition on the rising edge of the 11th SCLK pulse. Serial Data Input. The control byte is read in at this input. In order to complete a serial write operation 13 SCLK pulses need to be provided. Only the first 10 bits are shifted in--see Serial Interface section. Serial Clock Input. An external serial clock is applied to this input to obtain serial data from the AD7811/AD7812 and also to latch data into the AD7811/AD7812. Data is clocked out on the rising edge of SCLK and latched in on the falling edge of SCLK. Convert Start. This is an edge triggered logic input. The Track/Hold goes into its Hold Mode on the falling edge of this signal and a conversion is initiated. The state of this pin at the end of conversion also determines whether the part is powered down or not. See operating modes section of this data sheet. Positive Supply Voltage 2.7 V to 5.5 V. 5
2 3, 57 4 8
2 3, 511 4 12
CREF VIN1VIN4(8) AGND A0
9 10 11
13 14 15
DGND TFS RFS
12
16
DOUT
13
17
DIN
14
18
SCLK
15
19
CONVST
16 REV. B
20
V DD
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