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Details, datasheet, quote on part number:AD7840BQ
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Datasheet text preview:
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FEATURES Complete 14-Bit Voltage Output DAC Parallel and Serial Interface Capability 80 dB Signal-to-Noise Ratio Interfaces to High Speed DSP Processors e.g., ADSP-2100, TMS32010, TMS32020 45 ns min WR Pulse Width Low Power 70 mW typ. Operates from 5 V Supplies
LC2MOS Complete 14-Bit DAC AD7840
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7840 is a fast, complete 14-bit voltage output D/A converter. It consists of a 14-bit DAC, 3 V buried Zener reference, DAC output amplifier and high speed control logic. The part features double-buffered interface logic with a 14-bit input latch and 14-bit DAC latch. Data is loaded to the input latch in either of two modes, parallel or serial. This data is then transferred to the DAC latch under control of an asynchronous LDAC signal. A fast data setup time of 21 ns allows direct parallel interfacing to digital signal processors and high speed 16-bit microprocessors. In the serial mode, the maximum serial data clock rate can be as high as 6 MHz. The analog output from the AD7840 provides a bipolar output range of ± 3 V. The AD7840 is fully specified for dynamic performance parameters such as signal-to-noise ratio and harmonic distortion as well as for traditional dc specifications. Full power output signals up to 20 kHz can be created. The AD7840 is fabricated in linear compatible CMOS (LC2MOS), an advanced, mixed technology process that combines precision bipolar circuits with low power CMOS logic. The part is available in a 24-pin plastic and hermetic dual-in-line package (DIP) and is also packaged in a 28-terminal plastic leaded chip carrier (PLCC).
1. Complete 14-Bit D/A Function The AD7840 provides the complete function for creating ac signals and dc voltages to 14-bit accuracy. The part features an on-chip reference, an output buffer amplifier and 14-bit D/A converter. 2. Dynamic Specifications for DSP Users In addition to traditional dc specifications, the AD7840 is specified for ac parameters including signal-to-noise ratio and harmonic distortion. These parameters along with important timing parameters are tested on every device. 3. Fast, Versatile Microprocessor Interface The AD7840 is capable of 14-bit parallel and serial interfacing. In the parallel mode, data setup times of 21 ns and write pulse widths of 45 ns make the AD7840 compatible with modern 16-bit microprocessors and digital signal processors. In the serial mode, the part features a high data transfer rate of 6 MHz.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
+5 V = DGND = O V, AD7840SPECIFICATIONS (CV ==100 pF. All5%, V = 5 V T 5%, TAGNDunless othewiseREF IN = +3 V, R = 2 k specifications to noted.)
DD SS L L MIN MAX
,
Parameter DYNAMIC PERFORMANCE2 Signal to Noise Ratio3 (SNR)
J, A1 76
K, B1 78 80 80
S1 76 78 78
Units dB min dB max dB max
Test Conditions/Comments VOUT = 1 kHz Sine Wave, fSAMPLE = 100 kHz Typically 82 dB at +25°C for 0 < VOUT < 20 kHz4 VOUT = 1 kHz Sine Wave, fSAMPLE = 100 kHz Typically 84 dB at +25°C for 0 < VOUT < 20 kHz4 VOUT = 1 kHz Sine Wave, fSAMPLE = 100 kHz Typically 84 dB at +25°C for 0 < VOUT < 20 kHz4
Total Harmonic Distortion (THD) 78 Peak Harmonic or Spurious Noise DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Bipolar Zero Error Positive Full Scale Error5 Negative Full Scale Error5 REFERENCE OUTPUT6 REF OUT @ +25°C REF OUT TC Reference Load Change (REF OUT vs. I) REFERENCE INPUT Reference Input Range Input Current LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Current (CS Input Only) Input Capacitance, CIN7 ANALOG OUTPUT Output Voltage Range DC Output Impedance Short-Circuit Current AC CHARACTERISTICS7 Voltage Output Settling Time Positive Full-Scale Change Negative Full-Scale Change Digital-to-Analog Glitch Impulse Digital Feedthrough POWER REQUIREMENTS VDD V SS I DD ISS Power Dissipation 78
14 ±2 ± 0.9 ± 10 ± 10 ± 10 2.99 3.01 ± 60 1 2.85 3.15 50 2.4 0.8 ± 10 ± 10 10 ±3 0.1 20
14 ±1 ± 0.9 ± 10 ± 10 ± 10 2.99 3.01 ± 60 1 2.85 3.15 50 2.4 0.8 ± 10 ± 10 10 ±3 0.1 20
14 ±2 ± 0.9 ± 10 ± 10 ± 10 2.99 3.01 ± 60 1 2.85 3.15 50 2.4 0.8 ± 10 ± 10 10 ±3 0.1 20
Bits LSB max LSB max LSB max LSB max LSB max V min V max ppm/°C max mV max V min V max µA max V min V max µA max µA max pF max V nom typ mA typ
Guaranteed Monotonic
Reference Load Current Change (0500 µA) 3 V ± 5%
VDD = 5 V ± 5% VDD = 5 V ± 5% VIN = 0 V to VDD VIN =VSS to VDD
4 4 10 2 +5 5 14 6 100
4 4 10 2 +5 5 14 6 100
4 4 10 2 +5 5 15 7 110
µs max µs max nV secs typ nV secs typ V nom V nom mA max mA max mW max
Settling Time to within ± 1/2 LSB of Final Value Typically 2 µs Typically 2.5 µs
± 5% for Specified Performance ± 5% for Specified Performance Output Unloaded, SCLK = +5 V. Typically 10 mA Output Unloaded, SCLK = +5 V. Typically 4 mA Typically 70 mW
NOTES 1 Temperature ranges are as follows: J, K Versions, 0°C to +70°C; A, B Versions, 25°C to +85°C; S Version, 55°C to +125°C. 2 VOUT (pk-pk) = ± 3 V 3 SNR calculation includes distortion and noise components. 4 Using external sample-and-hold (see Testing the AD7840). 5 Measured with respect to REF IN and includes bipolar offset error. 6 For capacitive loads greater than 50 pF, a series resistor is required (see Internal Reference section). 7 Sample tested @ +25°C to ensure compliance. Specifications subject to change without notice.
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AD7840 TIMING CHARACTERISTICS1, 2
Parameter t1 t2 t3 t4 t5 t6 t7 t8 3 t9 t10 t11 Limit at TMIN, TMAX (J, K, A, B Versions) 0 0 45 21 10 40 50 150 30 75 75
(VDD = +5 V
5%, VSS = 5 V
5%, AGND = DGND = 0 V.)
Units ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min Conditions/Comments CS to WR Setup Time CS to WR Hold Time WR Pulse Width Data Valid to WR Setup Time Data Valid to WR Hold Time LDAC Pulse Width SYNC to SCLK Falling Edge SCLK Cycle Time Data Valid to SCLK Setup Time Data Valid to SCLK Hold Time SYNC to SCLK Hold Time
Limit at TMIN, TMAX (S Version) 0 0 50 28 15 40 50 200 40 100 100
NOTES 1 Timing specifications in bold print are 100% production tested. All other times are sample tested at +25 °C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 See Figures 6 and 8. 3 SCLK mark/space ratio is 40/60 to 60/40. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
ORDERING GUIDE
Temperature Range 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 25°C to +85°C 25°C to +85°C 25°C to +85°C 55°C to +125°C SNR (dB) 78 min 80 min 78 min 80 min 78 min 78 min 80 min 78 min Integral Nonlinearity (LSB) ± 2 max ± 1 max ± 2 max ± 1 max ± 2 max ± 2 max ± 1 max ± 2 max Package Option2 N-24 N-24 P-28A P-28A Q-24 RS-24 Q-24 Q-24
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to 7 V AGND to DGND . . . . . . . . . . . . . . . . 0.3 V to VDD + 0.3 V VOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . 0 V to VDD REF IN to AGND . . . . . . . . . . . . . . . . 0.3 V to VDD + 0.3 V Digital Inputs to DGND . . . . . . . . . . . 0.3 V to VDD + 0.3 V Operating Temperature Range Commercial (J, K Versions) . . . . . . . . . . . . . . 0°C to +70°C Industrial (A, B Versions) . . . . . . . . . . . . . . 25°C to +85°C Extended (S Version) . . . . . . . . . . . . . . . . 55°C to +125°C Storage Temperature Range . . . . . . . . . . . . 65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Model1 AD7840JN AD7840KN AD7840JP AD7840KP AD7840AQ AD7840ARS AD7840BQ AD7840SQ3
NOTES 1 To order MIL-STD-883, Class B processed parts, add /883B to part number. Contact your local sales office for military data sheet and availability. 2 N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip. 3 This grade will be available to /883B processing only.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7840 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD7840
PIN FUNCTION DESCRIPTION
DIP Pin No. 1
Pin Mnemonic CS /SERIAL
Function Chip Select/Serial Input. When driven with normal logic levels, it is an active low logic input which is used in conjunction with WR to load parallel data to the input latch. For applications where CS is permanently low, an R, C is required for correct power-up (see LDAC input). If this input is tied to VSS, it defines the AD7840 for serial mode operation. Write/Frame Synchronization Input. In the parallel data mode, it is used in conjunction with CS to load parallel data. In the serial mode of operation, this pin functions as a Frame Synchronization pulse with serial data expected after the falling edge of this signal. Data Bit 13(MSB)/Serial Data. When parallel data is selected, this pin is the D13 input. In serial mode, SDATA is the serial data input which is used in conjunction with SYNC and SCLK to transfer serial data to the AD7840 input latch. Data Bit 12/Serial Clock. When parallel data is selected, this pin is the D12 input. In the serial mode, it is the serial clock input. Serial data bits are latched on the falling edge of SCLK when SYNC is low. Data Bit 11/Data Format. When parallel data is selected, this pin is the D11 input. In serial mode, a Logic 1 on this input indicates that the MSB is the first valid bit in the serial data stream. A Logic 0 indicates that the LSB is the first valid bit (see Table I). Data Bit 10/Data Justification. When parallel data is selected, this pin is the D10 input. In serial mode, this input controls the serial data justification (see Table I). Data Bit 9 to Data Bit 5. Parallel data inputs. Digital Ground. Ground reference for digital circuitry. Data Bit 4 to Data Bit 1. Parallel data inputs. Data Bit 0 (LSB). Parallel data input. Positive Supply, +5 V ± 5%. Analog Ground. Ground reference for DAC, reference and output buffer amplifier. Analog Output Voltage. This is the buffer amplifier output voltage. Bipolar output range (± 3 V with REF IN = +3 V). Negative Supply Voltage, 5 V ± 5%. Voltage Reference Output. The internal 3 V analog reference is provided at this pin. To operate the AD7840 with internal reference, REF OUT should be connected to REF IN. The external load capability of the reference is 500 µA. Voltage Reference Input. The reference voltage for the DAC is applied to this pin. It is internally buffered before being applied to the DAC. The nominal reference voltage for correct operation of the AD7840 is 3 V. Load DAC. Logic Input. A new word is loaded into the DAC latch from the input latch on the falling edge of this signal (see Interface Logic Information section). The AD7840 should be powered-up with LDAC high. For applications where LDAC is permanently low, an R, C is required for correct power-up (see Figure 19).
Table I. Serial Data Modes
2
W R /S Y N C
3
D13/SDATA
4 5
D12/SCLK D11/FORMAT
6 711 12 1316 17 18 19 20 21 22
D10/JUSTIFY D9D5 DGND D4D1 D0 V DD AGND V OUT V SS REF OUT
23
REF IN
24
LDAC
4
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AD7840
PIN CONFIGURATIONS DIP/SSOP PLCC
D/A SECTION
The AD7840 contains a 14-bit voltage mode D/A converter consisting of highly stable thin film resistors and high speed NMOS single-pole, double-throw switches. The simplified circuit diagram for the DAC section is shown in Figure 1. The three MSBs of the data word are decoded to drive the seven switches AG. The 11 LSBs switch an 11-bit R-2R ladder structure. The output voltage from this converter has the same polarity as the reference voltage, REF IN. The REF IN voltage is internally buffered by a unity gain amplifier before being applied to the D/A converter and the bipolar bias circuitry. The D/A converter is configured and sealed for a 3 V reference and the device is tested with 3 V applied to REF IN. Operating the AD7840 at reference voltages outside the ± 5% tolerance range may result in degraded performance from the part.
for external use, it should he decoupled to AGND with a 200 resistor in series with a parallel combination of a 10 µF tantalum capacitor and a 0.1 µF ceramic capacitor.
Figure 2. Internal Reference
EXTERNAL REFERENCE
In some applications, the user may require a system reference or some other external reference to drive the AD7840 reference input. Figure 3 shows how the AD586 5 V reference can be conditioned to provide the 3 V reference required by the AD7840 REF IN. An alternate source of reference voltage for the AD7840 in systems which use both a DAC and an ADC is to use the REF OUT voltage of ADCs such as the AD7870 and AD7871. A circuit showing this arrangement is shown in Figure 20.
Figure 1. DAC Ladder Structure
INTERNAL REFERENCE
The AD7840 has an on-chip temperature compensated buried Zener reference (see Figure 2) which is factory trimmed to 3 V ± 10 mV. The reference voltage is provided at the REF OUT pin. This reference can be used to provide both the reference voltage for the D/A converter and the bipolar bias circuitry. This is achieved by connecting the REF OUT pin to the REF IN pin of the device. The reference voltage can also be used as a reference for other components and is capable of providing up to 500 µA to an external load. The maximum recommended capacitance on REF OUT for normal operation is 50 pF. If the reference is required REV. B 5
Figure 3. AD586 Driving AD7840 REF IN
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