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Details, datasheet, quote on part number:AD7841
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| Part: | AD7841 |
| Category: | Data Conversion => DAC (Digital to Analog Converters) => >14 bit |
| Description: | Octal 14-Bit DACs on One Monolithic Chip |
| Company: | Analog Devices |
| Datasheet: | Download AD7841 datasheet File size : 170 kB |
| Request For quote: | Find where to buy AD7841
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Datasheet text preview:
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FEATURES Eight 14-Bit DACs in One Package Voltage Outputs Offset Adjust for Each DAC Pair Reference Range of 5 V Maximum Output Voltage Range of 10 V 15 V 10% Operation Clear Function to User-Defined Voltage 44-Lead MQFP Package APPLICATIONS Automatic Test Equipment Process Control General Purpose Instrumentation
Octal 14-Bit, Parallel Input, Voltage-Output DAC AD7841
GENERAL DESCRIPTION
The AD7841 contains eight 14-bit DACs on one monolithic chip. It has output voltages with a full-scale range of ± 10 V from reference voltages of ± 5 V. The AD7841 accepts 14-bit parallel loaded data from the external bus into one of the input registers under the control of the WR, CS, and DAC channel address pins, A0A2. The DAC outputs are updated on reception of new data into the DAC registers. All the outputs may be updated simultaneously by taking the LDAC input low. Each DAC output is buffered with a gain-of-two amplifier into which an external DAC offset voltage can be inserted via the DUTGNDx pins. The AD7841 is available in a 44-lead MQFP package.
FUNCTIONAL BLOCK DIAGRAM
VCC VSS VDD VREF(+) AB VREF() AB DUTGND CD DUTGND AB
AD7841
14 INPUT 14 REG A INPUT 14 REG B INPUT 14 REG C INPUT 14 REG D INPUT 14 REG E INPUT 14 REG F INPUT 14 REG G INPUT 14 REG H DAC 14 REG A DAC REG B 14 DAC B DAC A
R
R
VOUTA R R
DB13
14
VOUTB R
DB0 14 DAC REG C DAC REG D DAC REG E DAC REG F 14 DAC C R 14 14 DAC D R
VOUTC R
WR CS A0 A1 A2 LDAC 14 14 DAC F
ADDRESS DECODE
VOUTD
14
14 DAC E VOUTE R R
VOUTF 14 DAC REG G 14 DAC G VOUTG 14 DAC REG H 14 DAC H VOUTH R R R R R R
GND
VREF(+) VREF() GH GH
VREF(+) VREF() CDEF CDEF
CLR
DUTGND EF
DUTGND GH
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000
AD7841SPECIFICATIONS 0 V; R = 5 k
L
( V CC = 5 V
5%; VDD = 15 V 10%; VSS = 15 V 10%; GND = DUTGND = and CL = 50 pF to GND, TA1 = TMIN to TMAX, unless otherwise noted)
U nit Bits LSB max LSB max LSB max LSB max Test Conditions/Comments
Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Full-Scale Error Gain Error Gain Temperature Coefficient 2 DC Crosstalk2 REFERENCE INPUTS2 DC Input Impedance Input Current VREF(+) Range VREF() Range [VREF(+) VREF()] DUTGND INPUTS2 DC Input Impedance Max Input Current Input Range3
A 14 ±4 0.9/2 ±8 ±8 ±2 0.5 10 120 100 ±1 0/5 5/0 2/10
B 14 ±2 ±1 ±8 ±8 ±2 0.5 10 120 100 ±1 0/5 5/0 2/10
LSB typ ppm FSR/°C typ ppm FSR/°C max µV max See Terminology. Typically 75 µV M typ µA max V min/max V min/max V min/max
Guaranteed Monotonic Over Temperature for All Grades VREF(+) = +5 V, VREF() = 5 V. Typically within ± 2 LSB VREF(+) = +5 V, VREF() = 5 V. Typically within ± 2 LSB VREF(+) = +5 V, VREF() = 5 V
Per Input. Typically ± 0.03 µA
For Specified Performance. Can Go as Low as 0 V, but Performance Not Guaranteed
60 ± 0.3 2/+2
60 ± 0.3 2/+2 VSS + 2.5 V to VDD 2.5 V 15 5 50 0.5 2.4 0.8 ±1 ± 10 10 4.75/+5.25 15 V ± 10% 15 V ± 10% 90 90 0.5 10 10
k typ mA typ V min/max V typ mA max k min pF max max V min V max
Per Input
OUTPUT CHARACTERISTICS2 Output Voltage Swing VSS + 2.5 V to VDD 2.5 V Short Circuit Current 15 Resistive Load 5 Capacitive Load 50 DC Output Impedance 0.5 DIGITAL INPUTS2 VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current @ 25°C TMIN to TMAX CIN, Input Capacitance POWER REQUIREMENTS 4 V CC V DD V SS Power Supply Sensitivity2 Full Scale/VDD Full Scale/VSS I CC I DD I SS 2.4 0.8 ±1 ± 10 10 4.75/+5.25 15 V ± 10% 15 V ± 10% 90 90 0.5 10 10
VOUT = 2 × (VREF() + [VREF(+) VREF()] × D) V DUTGND To 0 V To 0 V
Total for All Pins µA max µA max pF max V min/max V min/max V min/max dB typ dB typ mA max mA max mA max For Specified Performance For Specified Performance For Specified Performance
VINH = VCC, VINL = GND. Dynamic Current Outputs Unloaded. Typically 8 mA Outputs Unloaded. Typically 8 mA
NOTES 1 Temperature range for A and B Versions: 40°C to +85°C. 2 Guaranteed by characterization. Not production tested. 3 See DUTGND Voltage Range section. 4 The AD7841 is functional with power supplies of ± 12 V ± 10% with reduced output range. Output amplifier requires 2.5 V of head room at the bottom and top ends of the transfer for function. At 12 V supplies it is recommended to restrict the reference range to ± 4 V. Specifications subject to change without notice.
2
REV. A
AD7841 AC PERFORMANCE CHARACTERISTICS
Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time A&B Versions 31 Unit µs typ V/µs typ nV-s typ
(These characteristics are included for Design Guidance and are not subject to production testing.)
Test Conditions/Comments Full-Scale Change to ± 1/2 LSB. DAC Latch Contents Alternately Loaded with All 0s and All 1s Measured with VREF(+) = +5 V, VREF() = 5 V. DAC Latch Alternately Loaded with 1FFF Hex and 2000 Hex. Not Dependent on Load Conditions See Terminology See Terminology Feedthrough to DAC Output Under Test Due to Change in Digital Input Code to Another Converter Effect of Input Bus Activity on DAC Output Under Test All 1s Loaded to DAC. VREF(+) = VREF() = 0 V
Slew Rate 0.7 Digital-to-Analog Glitch Impulse 230
Channel-to-Channel Isolation DAC-to-DAC Crosstalk Digital Crosstalk Digital Feedthrough Output Noise Spectral Density @ 1 kHz
Specifications subject to change without notice.
99 40 0.2 0.1 200
dB typ nV-s typ nV-s typ nV-s typ nV/Hz typ
TIMING SPECIFICATIONS1, 2 (V
Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 15 0 50 50 0 0 20 0 31 300 50
CC
=5V
5%; VDD = 15 V
Unit ns min ns min ns min ns min ns min ns min ns min ns min µs typ ns max ns min
10%; VSS = 15 V
10%; GND = DUTGND = 0 V)
Description Address to WR Setup Time Address to WR Hold Time CS Pulsewidth Low WR Pulsewidth Low CS to WR Setup Time WR to CS Hold Time Data Setup Time Data Hold Time Settling Time CLR Pulse Activation Time LDAC Pulsewidth Low
Limit at TMIN, TMAX
NOTES 1 All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 Rise and fall times should be no longer than 50 ns. Specifications subject to change without notice.
t1
A0, A1, A2
t2
t5
CS WR
t6 t3 t4 t7 t8
DATA
t9
VOUT
t10
CLR
VOUT
t11
LDAC
Figure 1. Timing Diagram
REV. A
3
AD7841
ABSOLUTE MAXIMUM RATINGS 1, 2
(TA = 25°C unless otherwise noted)
VCC to GND3 . . . . . . . . . . . . . . 0.3 V, +7 V or VDD + 0.3 V (Whichever Is Lower) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, +17 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, 17 V Digital Inputs to GND . . . . . . . . . . . . . . 0.3 V, VCC + 0.3 V VREF(+) to VREF() . . . . . . . . . . . . . . . . . . . . . 0.3 V, +18 V VREF(+) to GND . . . . . . . . . . . . . . . VSS 0.3 V, VDD + 0.3 V VREF() to GND . . . . . . . . . . . . . . . VSS 0.3 V, VDD + 0.3 V DUTGND to GND . . . . . . . . . . . . . VSS 0.3 V, VDD + 0.3 V VOUT (AH) to GND . . . . . . . . . . . . VSS 0.3 V, VDD + 0.3 V Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . 40°C to +85°C Storage Temperature Range . . . . . . . . . . . . 65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C MQFP Package Power Dissipation . . . . . . . . . . . . . . . . . (TJ Max TA)/JA JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 95°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4000 V
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up. 3 V CC must not exceed VDD by more than 0.3 V. If it is possible for this to happen during power supply sequencing, the following diode protection scheme will ensure protection.
VDD IN4148 VCC HP5082-2811 VDD VCC
AD7841
ORDERING GUIDE
Model AD7841AS AD7841BS
Temperature Range 40°C to +85°C 40°C to +85°C
Linearity Error (LSBs) ±4 ±2
DNL (LSBs) 0.9/+2 ±1
Package Description Plastic Quad Flatpack (MQFP) Plastic Quad Flatpack (MQFP)
Package Option S-44 S-44
PIN CONFIGURATION
DUTGND_CD VREF()CDEF VREF(+)CDEF
DUTGND_EF
VOUTC
VOUTB
VOUTD
VOUTE
44 43
42
41
40
39
38
37
36
35
VOUTF
34 33 DUTGND_GH
DUTGND_AB 1 VOUTA
2 PIN 1 IDENTIFIER
VOUTG
32 VOUTH 31 VREF()GH 30 VREF(+)GH 29 CLR 28 DB13 27 DB12 26 DB11 25 DB10 24 DB9 23 DB8 22
VREF()AB 3 VREF(+)AB 4 VDD VSS LDAC A2 A1
5 6 7 8 9
AD7841
TOP VIEW (Not to Scale)
A0 10 CS 11
12 13 14 15 16 17 18 19 20 21
DB1
WR
DB2
DB3
VCC
VDD
DB6
DB0
GND
DB4
DB5
DB7
4
REV. A
AD7841
PIN FUNCTION DESCRIPTIONS
Pin No. 1 2, 44, 43, 41, 37, 35, 34, 32 3, 4 5, 38 6 7
Mnemonic DUTGND_AB VOUTA . . VOUTH
Description Device Sense Ground for DACs A and B. VOUTA and VOUTB are referenced to the voltage applied to this pin. DAC Outputs.
VREF()AB, VREF(+)AB V DD V SS LDAC
8, 9, 10 11 12
A2, A1, A0 CS WR
13 14 1528 29
V CC GND D B0 . . DB12 CLR
30, 31 33 36 39 40 42
VREF(+)GH, VREF()GH DUTGND_GH DUTGND_EF V REF(+)CDEF V REF()CDEF DUTGND_CD
Reference Inputs for DACs A and B. These reference voltages are referred to GND. Positive Analog Power Supply; +15 V ± 10% for specified performance. Negative Analog Power Supply; 15 V ± 10% for specified performance. Load DAC Logic Input (active low). When this logic input is taken low the contents of the registers are transferred to their respective DAC registers. LDAC can be tied permanently low enabling the outputs to be updated on the rising edge of WR. Address inputs. A0, A1 and A2 are decoded to select one of the eight input registers for a data transfer. Level-Triggered Chip Select Input (active low). The device is selected when this input is low. Level-Triggered Write Input (active low), used in conjunction with CS to write data to the AD7841 data registers. Data is latched into the selected input register on the rising edge of WR. Logic Power Supply; 5 V ± 5%. Ground. Parallel Data Inputs. The AD7841 can accept a straight 14-bit parallel word on DB0 to DB13 where DB13 is the MSB and DB0 is the LSB. Asynchronous Clear Input (level sensitive, active low). When this input is low, all analog outputs are switched to the externally set potential on the relevant DUTGND pin. The contents of input registers and DAC registers A to H are not affected when the CLR pin is taken low. When CLR is brought back high, the DAC outputs revert to their original outputs as determined by the data in their DAC registers. Reference Inputs for DACs G and H. These reference voltages are referred to GND. Device Sense Ground for DACs G and H. VOUTG and VOUTH are referenced to the voltage applied to this pin. Device Sense Ground for DACs E and F. VOUTE and VOUTF are referenced to the voltage applied to this pin. Reference Inputs for DACs C, D, E and F. These reference voltages are referred to GND. Reference Inputs for DACs C, D, E and F. These reference voltages are referred to GND. Device Sense Ground for DACs C and D. VOUTC and VOUTD are referenced to the voltage applied to this pin.
REV. A
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