|
Details, datasheet, quote on part number:AD7843ARU
| |
Datasheet text preview:
a
FEATURES 4-Wire Touch Screen Interface Specified Throughput Rate of 125 kSPS Low Power Consumption: 1.37 mW Max at 125 kSPS with VCC = 3.6 V Single Supply, VCC of 2.2 V to 5.25 V Ratiometric Conversion High-Speed Serial Interface Programmable 8- or 12-Bit Resolution Two Auxiliary Analog Inputs Shutdown Mode: 1 A max 16-Lead QSOP and TSSOP Packages APPLICATIONS Personal Digital Assistants Smart Hand-Held Devices Touch Screen Monitors Point-of-Sales Terminals Pagers
X+ X Y+ Y
Touch Screen Digitizer AD7843
FUNCTIONAL BLOCK DIAGRAM
+VCC PENIRQ
AD7843
PEN INTERRUPT
T/H 4-TO-1 I/P MUX
IN3 IN4 VREF CHARGE REDISTRIBUTION DAC
COMP
GND
+VCC SAR + ADC CONTROL LOGIC
SPORT
GENERAL DESCRIPTION
The AD7843 is a 12-bit successive-approximation ADC with a synchronous serial interface and low on resistance switches for driving touch screens. The part operates from a single 2.2 V to 5.25 V power supply and features throughput rates greater than 125 kSPS. The external reference applied to the AD7843 can be varied from 1 V to +VCC, while the analog input range is from 0 V to VREF. The device includes a shutdown mode that reduces the current consumption to less than 1 µA. The AD7843 features on-board switches. This coupled with low power and high-speed operation make this device ideal for battery-powered systems such as personal digital assistants with resistive touch screens and other portable equipment. The part is available in a 16-lead 0.15" Quarter Size Outline (QSOP) package and a 16-lead Thin Shrink Small Outline (TSSOP) package.
DIN
CS
DOUT
DCLK
BUSY
PRODUCT HIGHLIGHTS
1. Ratiometric conversion mode available eliminating errors due to on-board switch resistances. 2. Maximum current consumption of 380 µA while operating at 125 kSPS. 3. Power-down options available. 4. Analog input range from 0 V to VREF. 5. Versatile serial I/O port.
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000
AD7843SPECIFICATIONS 40 C to +85 C, unless otherwise noted.)
Parameter DC ACCURACY Resolution No Missing Codes Integral Nonlinearity2 Offset Error2 Offset Error Match3 Gain Error2 Gain Error Match3 Power Supply Rejection SWITCH DRIVERS On-Resistance2 Y+, X+ Y, X ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance REFERENCE INPUT VREF Input Voltage Range DC Leakage Current VREF Input Impedance VREF Input Current3 AD7843A1 12 11 ±2 ±6 1 0.1 ±4 1 0.1 70 Unit Bits Bits min LSB max LSB max LSB max LSB typ LSB max LSB max LSB typ dB typ
(VCC = 2.7 V to 3.6 V, VREF = 2.5 V, fSCLK = 2 MHz unless otherwise noted; TA =
Test Conditions/Comments
VCC = 2.7 V
5 6 0 to VREF ± 0.1 37 1 . 0 / + VC C ±1 5 20 1 1 2.4 0.4 ±1 10
typ typ Volts µA typ pF typ V min/max µA max G typ µA max µA typ µA max V min V max µA max pF max
CS = GND or +VCC 8 µA typ fSAMPLE = 12.5 kHz CS = +VCC; 0.001 µA typ
LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN4 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL PENIRQ Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance4 Output Coding CONVERSION RATE Conversion Time Track/Hold Acquisition Time Throughput Rate POWER REQUIREMENTS VCC (Specified Performance) I C C5 Normal Mode (fSAMPLE = 125 kSPS) Normal Mode (fSAMPLE = 12.5 kSPS) Normal Mode (Static) Shutdown Mode (Static) Power Dissipation5 Normal Mode (fSAMPLE = 125 kSPS) Shutdown
NOTES 1 Temperature range as follows: A Version: 40°C to +85°C. 2 See Terminology. 3 Guaranteed by design. 4 Sample tested @ 25°C to ensure compliance. 5 See Power vs. Throughput Rate section. Specifications subject to change without notice.
Typically 10 nA, VIN = 0 V or +VCC
VCC 0.2 V min 0.4 V max 0.4 V max ± 10 µA max 10 pF max Straight (Natural) Binary 12 3 125 2.7/3.6 380 170 150 1 1.368 3.6 DCLK Cycles max DCLK Cycles min kSPS max V min/max µA max µA typ µA typ µA max mW max µW max
ISOURCE = 250 µA; VCC = 2.2 V to 5.25 V ISINK = 250 µA ISINK = 250 µA; 100 k Pull-Up
Functional from 2.2 V to 5.25 V Digital I/Ps = 0 V or VCC VCC = 3.6 V, 240 µA typ VCC = 2.7 V, fDCLK = 2 00 kHz VCC = 3.6 V VCC = 3.6 V VCC = 3.6 V
2
REV. 0
AD7843 TIMING SPECIFICATIONS1
Parameter fD C L K tACQ t1 t2 t3 3 t4 t5 t6 t7 t8 t9 3 t10 t11 t12 4
2
(TA = TMIN to TMAX, unless otherwise noted; VCC = 2.7 V to 3.6 V, VREF = 2.5 V)
Unit kHz min MHz max µs min ns min ns max ns max ns min ns min ns max ns min ns min ns max ns min ns max ns max Description
Limit at TMIN, TMAX 10 2 1.5 10 60 60 200 200 60 10 10 200 0 200 200
Acquisition Time CS Falling Edge to First DCLK Rising Edge CS Falling Edge to BUSY Three-State Disabled CS Falling Edge to DOUT Three-State Disabled DCLK High Pulsewidth DCLK Low Pulsewidth DCLK Falling Edge to BUSY Rising Edge Data Setup Time Prior to DCLK Rising Edge Data Valid to DCLK Hold Time Data Access Time after DCLK Falling Edge CS Rising Edge to DCLK Ignored CS Rising Edge to BUSY High Impedance CS Rising Edge to DOUT High Impedance
NOTES 1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V CC) and timed from a voltage level of 1.6 V. 2 Mark/Space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 2.0 V. 4 t12 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 12, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. Specifications subject to change without notice.
200 A
IOL
TO OUTPUT PIN
1.6V CL 50pF 200 A IOH
Figure 1. Load Circuit for Digital Output Timing Specifications
REV. 0
3
AD7843
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25°C unless otherwise noted)
+VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V Analog Input Voltage to GND . . . . . . . 0.3 V to VCC + 0.3 V Digital Input Voltage to GND . . . . . . . 0.3 V to VCC + 0.3 V Digital Output Voltage to GND . . . . . 0.3 V to VCC + 0.3 V VREF to GND . . . . . . . . . . . . . . . . . . . . 0.3 V to VCC + 0.3 V Input Current to Any Pin Except Supplies2 . . . . . . . ± 10 mA Operating Temperature Range Commercial . . . . . . . . . . . . . . . . . . . . . . . . 40°C to +85°C Storage Temperature Range . . . . . . . . . . . 65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
QSOP, TSSOP Package, Power Dissipation . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . 149.97°C/W (QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150.4°C/W (TSSOP) JC Thermal Impedance . . . . . . . . . . . . . 38.8°C/W (QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.6°C/W (TSSOP) Lead Temperature, Soldering Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTES 1 Stresses above those listed under Absolute Maximum Rating may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
Model AD7843ARQ AD7843ARQ-REEL AD7843ARQ-REEL7 AD7843ARU AD7843ARU-REEL AD7843ARU-REEL7 EVAL-AD7843CB3 EVAL-CONTROL BRD24
Temperature Range 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C Evaluation Board Controller Board
Linearity Error (LSB)1 ±2 ±2 ±2 ±2 ±2 ±2
Package Option R Q - 1 62 R Q - 1 62 R Q - 1 62 RU-16 RU-16 RU-16
Package Description QSOP QSOP QSOP TSSOP TSSOP TSSOP
Branding Information AD7843ARQ AD7843ARQ AD7843ARQ AD7843ARU AD7843ARU AD7843ARU
NOTES 1 Linearity error here refers to integral linearity error. 2 RQ = 0.15" Quarter Size Outline Package. 3 This can be used as a stand-alone evaluation board or in conjunction with the EVALUATION BOARD CONTROLLER for evaluation/demonstration purposes. 4 This EVALUATION BOARD CONTROLLER is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7843 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION QSOP/TSSOP
+VCC 1 X+ 2 Y+ 3 X 4
16 DCLK 15 CS 14 DIN
13 BUSY TOP VIEW Y 5 (Not to Scale) 12 DOUT
AD7843
GND 6 IN3 7 IN4 8
11 PENIRQ 10 +VCC 9
VREF
4
REV. 0
AD7843
PIN FUNCTION DESCRIPTIONS
Pin No. 1, 10 2 3 4 5 6 7 8 9 11 12
Mnemonic + VC C X+ Y+ X Y GND I N3 I N4 V REF PENIRQ DOUT
Function Power Supply Input. The +VCC range for the AD7843 is from 2.2 V to 5.25 V. Both +VCC pins should be connected directly together. X+ Position Input. ADC Input Channel 1. Y+ Position Input. ADC Input Channel 2. X Position Input. Y Position Input. Analog Ground. Ground reference point for all circuitry on the AD7843. All analog input signals and any external reference signal should be referred to this GND voltage. Auxiliary Input 1. ADC Input Channel 3. Auxiliary Input 2. ADC Input Channel 4. Reference Input for the AD7843. An external reference must be applied to this input. The voltage range for the external reference is 1.0 V to +VCC. For specified performance it is 2.5 V. Pen Interrupt. CMOS Logic open drain output (requires 10 k to 100 k pull-up resistor externally). Data Out. Logic Output. The conversion result from the AD7843 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the DCLK input. This output is high impedance when CS is high. BUSY Output. Logic Output. This output is high impedance when CS is high. Data In. Logic Input. Data to be written to the AD7843's Control Register is provided on this input and is clocked into the register on the rising edge of DCLK (see Control Register section). Chip Select Input. Active Low Logic Input. This input provides the dual function of initiating conversions on the AD7843 and also enables the serial input/output register. External Clock Input. Logic Input. DCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the AD7843's conversion process.
13 14 15 16
BUSY DIN CS DCLK
TERMINOLOGY Integral Nonlinearity
Gain Error
This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition.
Differential Nonlinearity
This is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e., VREF 1 LSB) after the offset error has been adjusted out.
Track/Hold Acquisition Time
This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.
Offset Error
The track/hold amplifier enters the acquisition phase on the fifth falling edge of DCLK after the START bit has been detected. Three DCLK cycles are allowed for the Track/Hold acquisition time and the input signal will be fully acquired to the 12-bit level within this time even with the maximum specified DCLK frequency. See Analog Input section for more details.
On-Resistance
This is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e., AGND + 1 LSB.
This is a measure of the ohmic resistance between the drain and source of the switch drivers.
REV. 0
5
|
|
