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Details, datasheet, quote on part number:AD7845SE/883B
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FEATURES 12-Bit CMOS MDAC with Output Amplifier 4-Quadrant Multiplication Guaranteed Monotonic (TMIN to T MAX) Space-Saving 0.3" DIPs and 24- or 28-Terminal Surface Mount Packages Application Resistors On Chip for Gain Ranging, etc. Low Power LC 2MOS APPLICATIONS Automatic Test Equipment Digital Attenuators Programmable Power Supplies Programmable Gain Amplifiers Digital-to-420 mA Converters
LC2MOS Complete 12-Bit Multiplying DAC AD7845
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7845 is the industry's first 4-quadrant multiplying D/A converter with an on-chip amplifier. It is fabricated on the LC2MOS process, which allows precision linear components and digital circuitry to be implemented on the same chip. The 12 data inputs drive latches which are controlled by standard CS and WR signals, making microprocessor interfacing simple. For stand-alone operation, the CS and WR inputs can be tied to ground, making all latches transparent. All digital inputs are TTL and 5 V CMOS compatible. The output amplifier can supply ± 10 V into a 2 k load. It is internally compensated, and its input offset voltage is low due to laser trimming at wafer level. For normal operation, RFB is tied to VOUT, but the user may alternatively choose RA, RB or RC to scale the output voltage range.
1. Voltage Output Multiplying DAC The AD7845 is the first DAC which has a full 4-quadrant multiplying capability and an output amplifier on chip. All specifications include amplifier performance. 2. Matched Application Resistors Three application resistors provide an easy facility for gain ranging, voltage offsetting, etc. 3. Space Saving The AD7845 saves space in two ways. The integration of the output amplifier on chip means that chip count is reduced. The part is housed in skinny 24-lead 0.3" DIP, 28-terminal LCC and PLCC and 24-terminal SOIC packages.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999
AD7845SPloadCI2FICApF.IAll specifications T= +15 TV, E = k , 100 T ONS1 (V to V connected to R . V
DD OUT FB OUT MIN
5%, VSS = 15 V,
S Version 12 ±1 ±1 ±1 ±2 ±4 ±5 ±3 ±6 ±6 ±7 ±2
5%, VREF = +10 V, AGND = DGND = O V,
Units Bits LSB max LSB max LSB max mV max mV max µV/ °C typ LSB max LSB max LSB max LSB max Test Conditions/Comments 1 LSB =
MAX unless otherwise noted.)
Parameter ACCURACY Resolution Relative Accuracy at +25°C TMIN to T MAX Differential Nonlinearity Zero Code Offset Error at +25°C TMIN to T MAX Offset Temperature Coefficient; (Offset/ Temperature) 2 Gain Error
J Version 12 ±1 ±1 ±1 ±2 ±3 ±5 ±3 ±6 ±6 ±7
K Version 12 ± 1/2 ± 3/4 ±1 ±1 ±2 ±5 ±2 ±6 ±6 ±7 ±2
A Version 12 ±1 ±1 ±1 ±2 ±3 ±5 ±3 ±6 ±6 ±7 ±2
B Version 12 ± 1/2 ± 3/4 ±1 ±1 ±2 ±5 ±2 ±6 ±6 ±7 ±2
T Version 12 ± 1/2 ± 3/4 ±1 ±1 ±3 ±5 ±2 ±6 ±6 ±7 ±2
VREF 2 12
= 2.4 mV
All Grades Are Guaranteed Monotonic over Temperature DAC Register Loaded with All 0s.
RFB, VOUT Connected RC, VOUT Connected, VREF = +5 V RB, VOUT Connected, VREF = +5 V RA, VOUT Connected, VREF = +2.5 V
Gain Temperature Coefficient; ±2 (Gain/ Temperature) 2 REFERENCE INPUT Input Resistance, Pin 17 APPLICATION RESISTOR RATIO MATCHING DIGITAL INPUTS VIH (Input High Voltage) VIL (Input Low Voltage) IIN (Input Current) CIN (Input Capacitance) 2 POWER SUPPLY4 VDD Range VSS Range Power Supply Rejection Gain/VDD Gain/VSS IDD ISS
ppm of FSR/°C RFB, VOUT Connected typ k min k max % max V min V max µA max pF max V min/V max V min/V max % per % max % per % max mA max mA max VDD = +15 V ± 5%, VREF = 10 V VSS = 15 V ± 5%. VOUT Unloaded VOUT Unloaded Typical Input Resistance = 12 k
8 16 0.5 2.4 0.8 ±1 7
8 16 0.5 2.4 0.8 ±1 7
8 16 0.5 2.4 0.8 ±1 7
8 16 0.5 2.4 0.8 ±1 7
8 16 0.5 2.4 0.8 ±1 7
8 16 05 2.4 0.8 ±1 7
Matching Between RA, RB, RC
Digital Inputs at 0 V and V DD
14.25/15.75 14.25/15.75 14.25/15.75 14.25/15.75 14.25/15.75 14.25/15.75 14.25/15.75 14.25/15.75 ± 0.01 ± 0.01 6 4 ± 0.01 ± 0.01 6 4 ± 0.01 ± 0.01 6 4 ± 0.01 ± 0.01 6 4
14.25/15.75 14.25/15.75 14.25/15.75 14.25/15.75 ± 0.01 ± 0.01 6 4 ± 0.01 ± 0.01 6 4
AC PERFORMANCE CHARACTERISTICS
DYNAMIC PERFORMANCE Output Voltage Settling Time 5 5 5
These characteristics are included for Design Guidance and are not subject to test.
5 5 5 µs max To 0.01% of Full-Scale Range VOUT Load = 2 k, 100 pF. DAC Register Alternately Loaded with All 0s and All 1s. Typically 2.5 µs at 25°C. VOUT Load = 2 k, 100 pF. Measured with V REF = 0 V. DAC Register Alternately Loaded with All 0s and All 1s. VREF = ±10 V, 10 kHz Sine Wave DAC Register Loaded with All 0s. VOUT, RFB Connected. DAC Loaded with All 1s VREF = 100 mV p-p Sine Wave. VOUT, RFB Connected. DAC Loaded with All 1s. VREF = 20 V p-p Sine Wave. R L = 2 k. VREF = 6 V rms, 1 kHz Sine Wave. VOUT, RFB Not Connected VOUT = ±10 V, RL = 2 k RL = 2 k, CL = 100 pF RFB, VOUT Connected, VOUT Shorted to AGND Includes Noise Due to Output Amplifier and Johnson Noise of RFB
Slew Rate Digital-to-Analog Glitch Impulse Multiplying Feedthrough Error3 Unity Gain Small Signal Bandwidth
11 55
11 55
11 55
11 55
11 55
11 55
V/µs typ nVs typ
5
5
5
5
5
5
mV p-p typ
600
600
600
600
600
600
kHz typ
Full Power Bandwidth
175
175
175
175
175
175
kHz typ
Total Harmonic Distortion
90
90 85 ± 10 0.2 11 2 250 100 50 50 50
90 85 ± 10 0.2 11 2 250 100 50 50 50
90 85 ± 10 0.2 11 2 250 100 50 50 50
90 85 ± 10 0.2 11 2 250 100 50 50 50
90 85 ± 10 0.2 11 2 250 100 50 50 50
dB typ dB min V min typ mA typ µV rms typ nV/Hz typ nV/Hz typ nV/Hz typ nV/Hz typ nV/Hz typ
OUTPUT CHARACTERISTICS5 Open Loop Gain 85 Output Voltage Swing Output Resistance Short Circuit Current @ +25°C Output Noise Voltage (0.1 Hz to 10 Hz) @ +25°C f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz f = 100 kHz ± 10 0.2 11 2 250 100 50 50 50
NOTES 1Temperature ranges are as follows: J, K Versions: 0°C to +70°C; A, B Versions: 40°C to +85°C; S, T Versions: 55°C to +125°C. 2Guaranteed by design and characterization, not production tested. 3The metal lid on the ceramic D-24A package is connected to Pin 12 (DGND). 4The device is functional with a power supply of ± 12 V. 5Minimum specified load resistance is 2 k. Specifications subject to change without notice.
2
REV. B
AD7845 TIMING CHARACTERISTICS1 (V
Parameter tCS tCH tWR tDS tDH 30 0 30 80 0
DD
= +15 V,
5%. VSS = 15 V,
Units ns min ns min ns min ns min ns min
5%. VREF = +10 V. AGND = DGND = O V.)
Test Conditions/Comments Chip Select to Write Setup Time Chip Select to Write Hold Time Write Pulsewidth Data Setup Time Data Hold Time
Limit at TMIN to TMAX (All Versions)
NOTES 1 Guaranteed by design and characterization, not production tested. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25°C unless otherwise stated)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . .0.3 V to +17 V VSS to DGND . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to 17 V VREF to AGND . . . . . . . . . . . . . . . . VDD + 0.3 V, VSS 0.3 V VRFB to AGND . . . . . . . . . . . . . . . . VDD + 0.3 V, VSS 0.3 V VRA to AGND . . . . . . . . . . . . . . . . . VDD + 0.3 V, VSS 0.3 V VRB to AGND . . . . . . . . . . . . . . . . . VDD + 0.3 V, VSS 0.3 V VRC to AGND . . . . . . . . . . . . . . . . . VDD + 0.3 V, VSS 0.3 V VOUT to AGND2 . . . . . . . . . . . . . . . VDD + 0.3 V, VSS 0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, VDD Digital Input Voltage to DGND . . . . . 0.3 V to VDD + 0.3 V Power Dissipation (Any Package) To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 mW Derates above +75°C . . . . . . . . . . . . . . . . . . . . . 10 mW/°C
Operating Temperature Range Commercial (J, K Versions) . . . . . . . . . . . . . 0°C to +70°C Industrial (A, B Versions) . . . . . . . . . . . . 40°C to +85°C Extended (S, T Versions) . . . . . . . . . . . . 55° C to +125°C Storage Temperature Range . . . . . . . . . . . 65° C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Only one Absolute Maximum Rating may be applied at any one time. 2 VOUT may be shorted to AGND provided that the power dissipation of the package is not exceeded.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7845 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE1
WARNING!
ESD SENSITIVE DEVICE
Model2 AD7845JN AD7845KN AD7845JP AD7845KP AD7845JR AD7845KR AD7845AQ AD7845BQ AD7845AR AD7845BR AD7845SQ/883B AD7845TQ/883B AD7845SE/883B
Temperature Range 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C 55°C to +125°C 55°C to +125°C 55°C to +125°C
Relative Accuracy @ +25 C ± 1 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1 LSB
tCS
tCH
5V
Package Option3 N-24 N-24 P-28A P-28A R-24 R-24 Q-24 Q-24 R-24 R-24 Q-24 Q-24 E-28A
CS 0V tWR 5V WR 0V tDS tDH 5V DATA 0V NOTES 1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF +5V. tR = tF = 20ns. V +V 2. TIMING MEASUREMENT REFERENCE LEVEL IS IH 2 IL
Figure 1. AD7845 Timing Diagram
NOTES 1Analog Devices reserves the right to ship either ceramic (D-24A) or cerdip (Q-24) hermetic packages. 2To order MIL-STD-883, Class B processed parts, add /883B to part number. 3E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.
REV. B
3
AD7845
PIN CONFIGURATIONS DIP, SOIC LCC PLCC
TERMINOLOGY
LEAST SIGNIFICANT BIT DIGITAL-TO-ANALOG GLITCH IMPULSE
This is the analog weighting of 1 bit of the digital word in a V REF DAC. For the AD7845, 1 LSB = 12 . 2
RELATIVE ACCURACY
Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for both endpoints (i.e., offset and gain error are adjusted out) and is normally expressed in least significant bits or as a percentage of full-scale range.
DIFFERENTIAL NONLINEARITY
This is the amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-secs or nV-secs depending upon whether the glitch is measured as a current or voltage. The measurement takes place with VREF = AGND.
DIGITAL FEEDTHROUGH
When the DAC is not selected (i.e., CS is high) high frequency logic activity on the device digital inputs is capacitively coupled through the device to show up as noise on the VOUT pin. This noise is digital feedthrough.
MULTIPLYING FEEDTHROUGH ERROR
Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of +1 LSB max over the operating temperature range ensures monotonicity.
GAIN ERROR
This is ac error due to capacitive feedthrough from the VREF terminal to VOUT when the DAC is loaded with all 0s.
OPEN-LOOP GAIN
Gain error is a measure of the output error between an ideal DAC and the actual device output with all 1s loaded after offset error has been adjusted out. Gain error is adjustable to zero with an external potentiometer. See Figure 13.
ZERO CODE OFFSET ERROR
Open-loop gain is defined as the ratio of a change of output voltage to the voltage applied at the VREF pin with all 1s loaded in the DAC. It is specified at dc.
UNITY GAIN SMALL SIGNAL BANDWIDTH
This is the error present at the device output with all 0s loaded in the DAC. It is due to the op amp input offset voltage and bias current and the DAC leakage current.
TOTAL HARMONIC DISTORTION
This is the frequency at which the magnitude of the small signal voltage gain of the output amplifier is 3 dB below unity. The device is operated as a closed-loop unity gain inverter (i.e., DAC is loaded with all 1s).
OUTPUT RESISTANCE
This is the effective output source resistance.
FULL POWER BANDWIDTH
This is the ratio of the root-mean-square (rms) sum of the harmonics to the fundamental, expressed in dBs.
OUTPUT NOISE
This is the noise due to the white noise of the DAC and the input noise of the amplifier. 4
Full power bandwidth is specified as the maximum frequency, at unity closed-loop gain, for which a sinusoidal input signal will produce full output at rated load without exceeding a distortion level of 3%.
REV. B
Typical Performance CharacteristicsAD7845
Figure 2. Frequency Response, G = 1
Figure 3. Output Voltage Swing vs. Resistive Load
Figure 4. Noise Spectral Density
Figure 5. THD vs. Frequency
Figure 6. Typical AD7845 Linearity vs. Power Supply
Figure 7. Multiplying Feedthrough Error vs. Frequency
80 70 60 50 OUTPUT mV 40 30 20 10 0 10 20 0 2 4 6 8 10 12 14 16 TIME s 18 20
Figure 8. Unity Gain Inverter Pulse Response (Large Signal)
Figure 9. Unity Gain Inverter Pulse Response (Small Signal)
Figure 10. Digital-to-Analog Glitch Impulse (All 1s to All 0s Transition)
REV. B
5
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