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Details, datasheet, quote on part number:AD7864AS-2
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Datasheet text preview:
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FEATURES High Speed (1.65 s) 12-Bit ADC Four Simultaneously Sampled Inputs Four Track/Hold Amplifiers 0.35 s Track/Hold Acquisition Time 1.65 s Conversion Time per Channel HW/SW Select of Channel Sequence for Conversion Single Supply Operation Selection of Input Ranges: 10 V, 5 V for AD7864-1 2.5 V for AD7864-3 0 V to 2.5 V, 0 V to 5 V for AD7864-2 High Speed Parallel Interface Which Also Allows Interfacing to 3 V Processors Low Power, 90 mW Typ Power Saving Mode, 20 W Typ Overvoltage Protection on Analog Inputs APPLICATIONS AC Motor Control Uninterrupted Power Supplies Data Acquisition Systems Communications
4-Channel, Simultaneous Sampling, High Speed, 12-Bit ADC AD7864
FUNCTIONAL BLOCK DIAGRAM
AVDD STBY VIN1A VIN1B VIN2A VIN2B VIN3A VIN3B VIN4A VIN4B FRSTDATA BUSY EOC
CONVERSION CONTROL LOGIC TRACK/HOLD 4 SIGNAL SCALING SIGNAL SCALING MUX SIGNAL SCALING SIGNAL SCALING SOFTWARE LATCH DB0DB3 12-BIT ADC OUTPUT DATA REGISTERS
VREF
6k
VREF GND
DVDD VDRIVE
A 2.5V REFERENCE
DGND AGND RD DB11 DB0 CS WR
D7864
INT/EXT CLOCK SELECT
INT CLOCK
CONVST SL1 SL2 SL3 SL4 H/S SEL
CLKIN INT/EXT AGND AGND CLK
GENERAL DESCRIPTION
maximum throughput is 130 kSPS for the read during conversion sequence operation. The throughput rate for the read after conversion sequence operation will depend on the read cycle time of the processor. See Timing and Control section. The AD7864 is available in a small (0.3 sq. inch area) 44-lead MQFP.
PRODUCT HIGHLIGHTS
The AD7864 is a high speed, low power, 4-channel simultaneous sampling 12-bit A/D converter that operates from a single +5 V supply. The part contains a 1.65 µs successive approximation ADC, four track/hold amplifiers, 2.5 V reference, on-chip clock oscillator, signal conditioning circuitry and a high speed parallel interface. The input signals on four channels are sampled simultaneously, thus preserving the relative phase information of the signals on the four analog inputs. The part accepts analog input ranges of ± 10 V, ± 5 V (AD7864-1), 0 V to 2.5 V, 0 V to 5 V for AD7864-2 and ± 2.5 V (AD7864-3). The part allows any subset of the four channels to be converted in order to maximize the throughput rate on the selected sequence. The channels to be converted can be selected via either hardware (channel select input pins) or software (programming the channel select register). A single conversion start signal (CONVST) simultaneously places all the track/holds into hold and initiates conversion sequence for the selected channels. The EOC signal indicates the end of each individual conversion in the selected conversion sequence. The BUSY signal indicates the end of the conversion sequence. Data is read from the part by means of a 12-bit parallel data bus using the standard CS and RD signals. Maximum throughput for a single channel is 500 kSPS. For all four channels the REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
1. The AD7864 features four Track/Hold amplifiers and a fast (1.65 µs) ADC allowing simultaneous sampling and then conversion of any subset of the four channels. 2. The AD7864 operates from a single +5 V supply and consumes only 90 mW typ making it ideal for low power and portable applications. Also see Standby Mode Operation. 3. The part offers a high speed parallel interface for easy connection to microprocessors, microcontrollers and digital signal processors. 4. The part is offered in three versions with different analog input ranges. The AD7864-1 offers the standard industrial input ranges of ± 10 V and ± 5 V; the AD7864-3 offers the common signal processing input range of ± 2.5 V; the AD7864-2 can be used in unipolar 0 V to 2.5 V, 0 V to 5 V applications. 5. The part features very tight aperture delay matching between the four input sample-and-hold amplifiers.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999
AD7864SPECIFICATIONS cations T
Parameter SAMPLE AND HOLD 3 dB Full Power Bandwidth Aperture Delay Aperture Jitter Aperture Delay Matching DYNAMIC PERFORMANCE2 Signal to (Noise + Distortion) Ratio3 @ +25°C TMIN to TMAX Total Harmonic Distortion3 Peak Harmonic or Spurious Noise3 Intermodulation Distortion3 2nd Order Terms 3rd Order Terms Channel-to-Channel Isolation3 DC ACCURACY Resolution Relative Accuracy3 Differential Nonlinearity3 AD7864-1 Positive Gain Error3 Positive Gain Error Match3 Negative Gain Error3 Negative Gain Error Match3 Bipolar Zero Error Bipolar Zero Error Match AD7864-3 Positive Gain Error3 Positive Gain Error Match3 Negative Gain Error3 Negative Gain Error Match3 Bipolar Zero Error Bipolar Zero Error Match AD7864-2 Positive Gain Error3 Positive Gain Error Match3 Unipolar Offset Error Unipolar Offset Error Match ANALOG INPUTS AD7864-1 Input Voltage Range Input Resistance AD7864-3 Input Voltage Range Input Resistance AD7864-2 Input Voltage Range Input Current (0 V2.5 V Option) Input Resistance (0 V5 V Option) REFERENCE INPUT/OUTPUT VREF IN Input Voltage Range VREF IN Input Capacitance4 VREF OUT Output Voltage VREF OUT Error @ +25°C VREF OUT Error TMIN to TMAX VREF OUT Temperature Coefficient VREF OUT Output Impedance A Version1 3 20 50 4
(VDD = +5 V
MIN
5%, AGND = DGND = 0 V, VREF = Internal. Clock = Internal; all specifito TMAX unless otherwise noted.)
B Version 3 20 50 4 Units MHz typ ns max ps typ ns max fIN = 100.0 kHz, fS = 500 kSPS Test Conditions/Comments
70 70 80 80 80 80 80 12 ±1 ± 0.9 ±3 3 ±3 3 ±4 2 ±3 2 ±3 2 ±3 2 ±3 3 ±3 2
72 70 80 80 80 80 80 12 ± 1/2 ± 0.9 ±3 ±3 ±3 ±3 ±3 ±2
dB min dB min dB max dB max fa = 49 kHz, fb = 50 kHz dB typ dB typ dB max Bits LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max
fIN = 50 kHz Sine Wave Any Channel
No Missing Codes
± 5, ± 10 9, 18 ± 2.5 4.5 +2.5, +5 ± 100 9 2.375/2.625 10 2.5 ± 10 ± 20 25 6
± 5, ± 10 9, 18 ± 2.5 4.5 +2.5, +5 ± 100 9 2.375/2.625 10 2.5 ± 10 ± 20 25 6
Volts k min Volts k min Volts nA max k min VMIN/VMAX pF max V nom mV max mV max ppm/° C typ k typ 2.5 V ± 5%
See Reference Section
2
REV. A
AD7864
Parameter LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN4 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL DB11DB0 High Impedance Leakage Current Capacitance4 Output Coding AD7864-1, AD7864-3 AD7864-2 CONVERSION RATE Conversion Time Track/Hold Acquisition Time2, 3 Throughput Time POWER REQUIREMENTS V DD I DD Normal Mode Standby Mode Power Dissipation Normal Mode Standby Mode A Version 2.4 0.8 ± 10 10 4.0 0.4 ± 10 10
1
B Version 2.4 0.8 ± 10 10 4.0 0.4 ± 10 10
Units V min V max µA max pF max V min V max µA max pF max
Test Conditions/Comments VDD = 5 V ± 5% VDD = 5 V ± 5%
ISOURCE = 400 µA ISINK = 1.6 mA
Twos Complement Straight (Natural) Binary 1.65 0.35 130 +5 24 20 120 100 1.65 0.35 130 +5 24 20 120 100 µs max µs max kSPS max V nom mA max µA max mW max µW max For One Channel For All Four Channels ± 5% for Specified Performance (5 µA typ) Logic Inputs = 0 V or VDD Typically 4 µA Typically 90 mW Typically 20 µW
NOTES 1 Temperature ranges are as follows: A, B Versions: 40°C to +85°C. Note: The A Version is fully specified up to +105°C with degraded INL and DNL specifications of ± 2 LSBs max. 2 Performance measured through full channel (SHA and ADC). 3 See Terminology. 4 Sample tested @ +25°C to ensure compliance. Specifications subject to change without notice.
REV. A
3
AD7864 TIMING CHARACTERISTICS1, 2
Parameter tCONV tACQ tBUSY tWAKE-UP--External VREF tWAKE-UP--Internal VREF3 t1 t2 Read Operation t3 t4 t5 t6 4 t7 5 t8 t9 t10 t11 t12 Write Operation t13 t14 t15 t16 t17
(VD = +5 V 5%, AGND = DGND = 0 V, V REF = Internal, Clock = Internal; all specifications TMIN to TMAX unless otherwise noted.)
Units µs max Clock Cycles µs max µs max µs max µs max ms max ns min ns min ns min ns min ns min ns max ns max ns min ns max ns min ns min ns max ns max ns max ns min ns min ns min ns min ns min ns min Test Conditions/Comments Conversion Time, Internal Clock Conversion Time, External Clock CLKIN = 5 MHz Acquisition Time Selected Number of Channels Multiplied by (tCONV + EOC Pulsewidth)--EOC Pulsewidth STBY Rising Edge to CONVST Rising Edge STBY Rising Edge to CONVST Rising Edge CONVST Pulsewidth CONVST Rising Edge to BUSY Rising Edge CS to RD Setup Time CS to RD Hold Time Read Pulsewidth Data Access Time After Falling Edge of RD, VDRIVE = 5 V Data Access Time After Falling Edge of RD, VDRIVE = 3 V Bus Relinquish Time After Rising Edge of RD Time Between Consecutive Reads EOC Pulsewidth RD Rising Edge to FRSTDATA Edge (Rising or Falling) EOC Falling Edge to FRSTDATA Falling Delay EOC to RD Delay WR Pulsewidth CS to WR Setup Time WR to CS Hold Time Input Data Setup Time of Rising Edge of WR Input Data Hold Time
A, B Versions 1.65 13 2.6 0.34 No. of Channels x (tCONV + t9) t9 2 6 35 70 0 0 35 35 40 5 30 10 75 180 70 15 0 20 0 0 5 5
NOTES 1 Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V. 2 See Figures 7, 8 and 9. 3 Refer to the Standby Mode Operation section. The MAX specification of 6 ms is valid when using a 0.1 µF decoupling capacitor on the V REF pin. 4 Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V. 5 These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. Specifications subject to change without notice.
1.6mA
TO OUTPUT 50pF 400 A
1.6V
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
4
REV. A
AD7864
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V Analog Input Voltage to AGND AD7864-1 (± 10 V Input Range) . . . . . . . . . . . . . . . . ± 20 V AD7864-1 (± 5 V Input Range) . . . . . . . . . . . 7 V to +20 V AD7864-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V to +20 V AD7864-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 V to +20 V Reference Input Voltage to AGND . . . 0.3 V to VDD + 0.3 V Digital Input Voltage to DGND . . . . . 0.3 V to VDD + 0.3 V Digital Output Voltage to DGND . . . . 0.3 V to VDD + 0.3 V Operating Temperature Range Commercial (A, B Version) . . . . . . . . . . . . 40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . 65° C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C MQFP Package, Power Dissipation . . . . . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 95°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD7864AS-1 AD7864BS-1 AD7864AS-3 AD7864AS-2
Input Ranges ± 5 V, ± 10 V ± 5 V, ± 10 V ± 2.5 V 0 V to 2.5 V, 0 V to 5 V
Relative Accuracy ± 1 LSB ± 0.5 LSB ± 1 LSB ± 1 LSB
Temperature Range* 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C
Package Description Plastic Lead Quad Flatpack Plastic Lead Quad Flatpack Plastic Lead Quad Flatpack Plastic Lead Quad Flatpack
Package Option S-44 S-44 S-44 S-44
*The A Version is fully specified up to +105°C with degraded INL and DNL specifications of ± 2 LSBs max.
PIN CONFIGURATION
DGND VDRIVE
DVDD
EOC
DB0
DB2
DB1
DB3
DB4
4 4 4 3 4 2 41 4 0 3 9 3 8 3 7 3 6 3 5 3 4 BUSY 1 FRSTDATA 2 CONVST 3 CS 4 RD 5 WR 6 SL1 7 SL2 8 SL3 9 SL4 10 H/S SEL 11 12 13 14 15 16 17 18 19 2 0 21 2 2 AGND AGND VIN3B VIN4A VIN4B VIN2B VIN2A VIN1B VIN1A STBY VIN3A
PIN 1 IDENTIFIER
DB5
DB6 3 3 DB7 3 2 DB8 31 DB9 3 0 DB10 2 9 DB11 2 8 CLKIN 2 7 INT/EXT CLK 2 6 AGND 2 5 AVDD 2 4 VREF 2 3 VREFGND
AD7864
TOP VIEW (Not to Scale)
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7864 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
5
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