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Details, datasheet, quote on part number:AD7866
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| Part: | AD7866 |
| Category: | Data Conversion => ADC (Analog to Digital Converters) => 10-14 bit => 12 bit |
| Description: | Dual 1MSPS, 12-Bit, 2-Channel Sar ADC With Serial Interface |
| Company: | Analog Devices |
| Datasheet: | Download AD7866 datasheet File size : 295 kB |
| Request For quote: | Find where to buy AD7866
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Datasheet text preview:
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FEATURES Dual 12-Bit, 2-Channel ADC Fast Throughput Rate 1 MSPS Specified for VDD of 2.7 V to 5.25 V Low Power 11.4 mW Max at 1 MSPS with 3 V Supplies 24 mW Max at 1 MSPS with 5 V Supplies Wide Input Bandwidth 70 dB SNR at 300 kHz Input Frequency Onboard Reference 2.5 V Flexible Power/Throughput Rate Management Simultaneous Conversion/Read No Pipeline Delays High-Speed Serial Interface SPI TM/QSPITM/ MICROWIRE TM/DSP Compatible Shut-Down Mode 1 A Max 20-Lead TSSOP Package
Dual 1 MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface AD7866
FUNCTIONAL BLOCK DIAGRAM
VREF DCAPA REF SELECT AVDD DVDD 2.5V REF VA1 VA2 BUF 12-BIT SUCCESSIVEAPPROXIMATION ADC
AD7866
OUTPUT DRIVERS DOUTA
MUX
T/H
CONTROL LOGIC
A0 RANGE SCLK CS VDRIVE
VB1 VB2
MUX
T/H
12-BIT SUCCESSIVEAPPROXIMATION ADC
OUTPUT DRIVERS
DOUT B
BUF
AGND
AGND
DCAPB
DGND
GENERAL DESCRIPTION
The AD7866 is a dual 12-bit high-speed, low power, successiveapproximation ADC. The part operates from a single 2.7 V to 5.25 V power supply and features throughput rates up to 1 MSPS. The device contains two ADCs, each preceded by a low-noise, wide bandwidth track/hold amplifier which can handle input frequencies in excess of 10 MHz. The conversion process and data acquisition are controlled using standard control inputs allowing easy interfacing to microprocessors or DSPs. The input signal is sampled on the falling edge of CS and conversion is also initiated at this point. The conversion time is determined by the SCLK frequency. There are no pipelined delays associated with the part. The AD7866 uses advanced design techniques to achieve very low power dissipation at high throughput rates. With 3 V supplies and 1 MSPS throughput rate, the part consumes a maximum of 3.8 mA. With 5 V supplies and 1 MSPS, the current consumption is a maximum of 4.8 mA. The part also offers flexible power/ throughput rate management when operating in sleep mode. The analog input range for the part can be selected to be a 0 V to VREF range or a 2 × VREF range with either straight binary or t w o ' s complement output coding. The AD7866 has an on-chip 2.5 V reference which can be overdriven if an external
reference is preferred. Each on-board ADC can also be supplied with a separate individual external reference. The AD7866 is available in a 20-lead thin shrink small outline (TSSOP) package.
PRODUCT HIGHLIGHTS
1. The AD7866 features two complete ADC functions allowing simultaneous sampling and conversion of two channels. Each ADC has a 2-channel input multiplexer. The conversion result of both channels is available simultaneously on separate data lines, or both may be taken on one data line if only one serial port is available. 2. High Throughput with Low Power Consumption--The AD7866 offers a 1 MSPS throughput rate with 11.4 mW maximum power consumption when operating at 3 V. 3. F l e x i b l e Power/Throughput Rate Management--The c o nversion rate is determined by the serial clock allowing the power consumption to be reduced as the conversion time is reduced through a SCLK frequency increase. Power efficiency can be maximized at lower throughput rates if the part enters sleep during conversions. 4. No Pipeline Delay--The part features two standard successiveapproximation ADCs with accurate control of the sampling instant via a CS input and once off conversion control.
SPI and QSPI are trademarks of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corporation.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002
to AD7866SPECIFICATIONS1 (ETxte=rnTal on DT
A MIN
MAX ,
CAPA
VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, Reference = 2.5 V and DCAPB, fSCLK = 20 MHz, unless otherwise noted.)
Unit dB min dB max dB max dB typ dB typ dB typ ns max ps typ ps max MHz typ MHz typ Bits LSB max L S B max LSB max LSB max LSB typ LSB max LSB typ LSB max LSB max LSB typ LSB max V V nA max pF typ pF typ V V min/V max µA max µA max pF typ V min/V max typ typ ppm/°C typ mV typ V min V max µA max pF max V min V max µA max pF max VREF to +VREF Biased about VREF with Two's Complement Output Coding Test Conditions/Comments fIN = 300 kHz Sine Wave, fS = 1 MSPS fIN = 300 kHz Sine Wave, fS = 1 MSPS fIN = 300 kHz Sine Wave, fS = 1 MSPS
Parameter DYNAMIC PERFORMANCE Signal to Noise + Distortion (SINAD)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second Order Terms Third Order Terms Channel to Channel Isolation SAMPLE AND HOLD Aperture Delay3 Aperture Jitter3 Aperture Delay Matching3 Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity 0 V to VREF Input Range Offset Error Offset Error Match Gain Error Gain Error Match 2 × VREF Input Range Positive Gain Error Zero Code Error Zero Code Error Match Negative Gain Error ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance REFERENCE INPUT/OUTPUT Reference Input Voltage Reference Input Voltage Range4 DC Leakage Current Input Capacitance Reference Output Voltage5 VREF Output Impedance6 Reference Temperature Coefficient REF OUT Error (TMIN to TMAX) LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN3 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding
A Version1 68 75 76 88 88 88 10 50 200 12 2 12 ± 1.5
B Version1 68 75 76 88 88 88 10 50 200 12 2
@ 3 dB @ 0.1 dB
12 ±1 ± 1.5 0.95/+1.25 0.95/+1.25 ±8 ± 1.2 ± 2.5 ± 0.2 ± 2.5 ±8 ± 0.2 ± 2.5 0 to VREF 0 to 2 × VREF ± 500 30 10 2.5 2/3 ± 30 ± 160 20 2.45/2.55 25 45 50 ± 15 0 . 7 V DRIVE 0 . 3 V DRIVE ±1 10
B Grade, 0 V to VREF range only; ±0.5 LSB typ 0 V to 2 × VREF range; ± 0.5 LSB typ Guaranteed No Missed Codes to 12 Bits Straight Binary Output Coding
±8 ± 1.2 ± 2.5 ± 0.2 ± 2.5 ±8 ± 0.2 ± 2.5 0 to VREF 0 to 2 × VREF ± 500 30 10 2.5 2/3 ± 30 ± 160 20 2.45/2.55 25 45 50 ± 15 0 . 7 V DRIVE 0 . 3 V DRIVE ±1 10
RANGE Pin Low upon CS Falling Edge RANGE Pin High upon CS Falling Edge When in Track When in Hold ± 1% for Specified Performance REF SELECT Pin Tied High VREF Pin; DCAPA, DCAPB Pins; VDD = 5 V VDD = 3 V
Typically 15 nA, VIN = 0 V or VDRIVE
VDRIVE 0.2 VDRIVE 0.2 0.4 0.4 ±1 ±1 10 10 Straight (Natural) Binary Two's Complement 2
ISOURCE = 200 µA ISINK = 200 µA VDD = 2.7 V to 5.25 V Selectable with Either Input Range REV. 0
AD7866
Parameter CONVERSION RATE Conversion Time Track/Hold Acquisition Time3 Throughput Rate POWER REQUIREMENTS V DD V DRIVE IDD 7 Normal Mode (Static) A Version1 16 300 1 2.7/5.25 2.7/5.25 3.1 2.8 Operational, fS = 1 MSPS 4.8 3.8 Partial Power-Down Mode Partial Power-Down Mode Full Power-Down Mode Power Dissipation7 Normal Mode (Operational) Partial Power-Down (Static) Full Power-Down (Static) 1.6 560 1 24 11.4 2.8 1.68 5 3 B Version1 16 300 1 2.7/5.25 2.7/5.25 3.1 2.8 4.8 3.8 1.6 560 1 24 11.4 2.8 1.68 5 3 Unit Test Conditions/Comments SCLK cycles 800 ns with SCLK = 20 MHz ns max MSPS max See Serial Interface Section V min/max V min/max mA max mA max mA max mA max mA max µA max µA max mW max mW max mW max mW max µW max µW max Digital I/Ps = 0 V or VDRIVE VDD = 4.75 V to 5.25 V. Add 0.5 mA Typical if Using Internal Reference VDD = 2.7 V to 3.6 V. Add 0.35 mA Typical if Using Internal Reference VDD = 4.75 V to 5.25 V. Add 0.5 mA Typical if Using Internal Reference VDD = 2.7 V to 3.6 V. Add 0.5 mA Typical if Using Internal Reference fS = 100 kSPS, fSCLK = 20 MHz Add 0.2 mA Typ if Using Internal Reference (Static) Add 100 µA Typical if Using Internal Reference SCLK On or Off. VDD = 5 V VDD = 3 V VDD = 5 V. SCLK On or Off. VDD = 3 V. SCLK On or Off. VDD = 5 V. SCLK On or Off. VDD = 3 V. SCLK On or Off.
NOTES 1 Temperature ranges as follows: A, B Versions: 40°C to +85°C. 2 See Terminology section. 3 Sample tested @ 25°C to ensure compliance. 4 External reference range that may be applied at V REF, DCAPA, or DCAPB. 5 Relates to pins VREF, DCAPA, or DCAPB. 6 See Reference section for D CAPA, DCAPB output impedances. 7 See Power Versus Throughput Rate section. Specifications subject to change without notice.
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AD7866 TIMING SPECIFICATIONS1 (V
Parameter fS C L K
2
DD
= 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.)
Limit at TMIN, TMAX 10 20 16 × tSCLK 800 50 10 25 40 0 . 4 tS C L K 0 . 4 tS C L K 10 25 10 50
Unit kHz min MHz max ns max ns max ns max ns min ns max ns max ns min ns min ns min ns max ns min ns max
Description
tCONVERT tQUIET t2 t3 3 t4 3 t5 t6 t7 t8 4 t9 4
tSCLK = 1/fSCLK fSCLK = 20 MHz Minimum Time Between End of Serial Read and Next Falling Edge of CS CS to SCLK Setup Time Delay from CS Until DOUTA and DOUTB Three-State Disabled Data Access Time After SCLK Falling Edge. VDRIVE 3 V, CL = 50 pF; VDRIVE < 3 V, CL = 25 pF SCLK Low Pulsewidth SCLK High Pulsewidth SCLK to Data Valid Hold Time CS Rising Edge to DOUTA, DOUTB, High Impedance SCLK Falling Edge to DOUTA, DOUTB, High Impedance SCLK Falling Edge to DOUTA, DOUTB, High Impedance
NOTES 1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DRIVE) and timed from a voltage level of 1.6 V. 2 Mark/Space ratio for the CLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V. 4 t8, t9 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times t 8 and t9 quoted in the timing characteristics are the true bus relinquish times of the part and are independent of the bus loading. Specifications subject to change without notice.
200 A
IOL
TO OUTPUT PIN
1.6V CL 50pF 200 A IOH
Figure 1. Load Circuit for Digital Output Timing Specifications
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25 C unless otherwise noted)
o
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V VDRIVE to DGND . . . . . . . . . . . . . . . 0.3 V to DVDD + 0.3 V VDRIVE to AGND . . . . . . . . . . . . . . . . 0.3 V to AVDD + 0.3 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . 0.3 V to +0.3 V Analog Input Voltage to AGND . . . . 0.3 V to AVDD + 0.3 V Digital Input Voltage to DGND . . . . . . . . . . . 0.3 V to +7 V VREF to AGND . . . . . . . . . . . . . . . . . 0.3 V to AVDD + 0.3 V Digital Output Voltage to DGND . . 0.3 V to VDRIVE + 0.3 V Input Current to Any Pin Except Supplies2 . . . . . . . . ± 10 mA Operating Temperature Range Commercial (A, B Versions) . . . . . . . . . . . . . 40oC to +85oC
Storage Temperature Range . . . . . . . . . . . . 65oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . 143°C/W (TSSOP) JC Thermal Impedance . . . . . . . . . . . . . 45°C/W (TSSOP) Lead Temperature, Soldering Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 kV
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch up.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7866 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD7866
ORDERING GUIDE
Model AD7866ARU AD7866BRU EVAL-AD7866CB1 EVAL-CONTROL BRD22
Temperature Range 40°C to +85°C 40°C to +85°C Evaluation Board Controller Board
Resolution (Bits) 12 12
Package Description Thin Shrink SO (TSSOP) Thin Shrink SO (TSSOP) (TSSOP)
Package Option RU-20 RU-20
NOTES 1 This can be used as a stand-alone evaluation board or in conjunction with the evaluation board controller for evaluation/demonstration purposes. 2 This evaluation board controller is a complete unit, allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
PIN CONFIGURATION
REF SELECT 1 DCAPB
2 20 A0 1 9 CS 1 8 SCLK 1 7 VDRIVE
AGND 3 VB2
4
VB1 5 VA2 6
AD7866
1 6 DOUTB
TOP VIEW 1 5 D OUTA (Not to Scale) VA1 7 1 4 DGND AGND 8 DCAPA 9 VREF 1 0
1 3 DVDD 1 2 AVDD 1 1 RANGE
PIN FUNCTION DESCRIPTIONS
Pin No. 1
Mnemonic REF SELECT
Function Internal/External Reference Selection Pin. Logic Input. If this pin is tied to GND, the on-chip 2.5 V reference is used as the reference source for both ADC A and ADC B. In addition, pins VREF, DCAPA, and DCAPB must be tied to decoupling capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the AD7866 through the VREF pin, in which case decoupling capacitors are required on DCAPA and DCAPB. However, if the VREF pin is tied to AGND while REF SELECT is tied to a logic low, an individual external reference can be applied to both ADC A and ADC B through pins DCAPA and DCAPB, respectively. See Reference section. Decoupling capacitors are connected to these pins to decouple the reference buffer for each respective ADC. The on-chip reference can be taken from these pins and applied externally to the rest of a system. Depending on the polarity of the REF SELECT pin and the configuration of the VREF pin, these pins can also be used to input a separate external reference to each ADC. The range of the external reference is dependent on the analog input range selected. See Reference section. Analog Ground. Ground reference point for all analog circuitry on the AD7866. All analog input signals and any external reference signal should be referred to this AGND voltage. Both of these pins should connect to the AGND plane of a system. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart even on a transient basis. Analog Inputs of ADC B. Single-ended analog input channels. The input range on each channel is 0 V to VREF or a 2 × VREF range depending on the polarity of the RANGE pin upon the falling edge of CS. Analog Inputs of ADC A. Single-ended analog input channels. The input range on each channel is 0 V to VREF or a 2 × VREF range depending on the polarity of the RANGE pin upon the falling edge of CS. Reference Decoupling Pin and External Reference Selection Pin. This pin is connected to the internal reference and requires a decoupling capacitor. The nominal reference voltage is 2.5 V and this appears at the pin; however, if the internal reference is to be used externally in a system, it must be taken from either the DCAPA or DCAPB pins. This pin is also used in conjunction with the REF SELECT pin when applying an external reference to the AD7866. See REF SELECT pin description.
2, 9
DCAPB, DCAPA
3, 8
AGND
4, 5 6, 7 10
VB2, VB1 VA2, VA1 V REF
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